Warning-[STASKW_CO] Cannot open file
/home/lightai/RISCV/RV12/bench/verilog/ahb3lite/memory_model_ahb3lite.sv, 149
The file 'test.hex' could not be opened. No such file or directory.
Please ensure that the file exists with proper permissions.
ERROR : Skip reading file test.hex. Reason file not found
$finish called from file "/home/lightai/RISCV/RV12/bench/verilog/ahb3lite/memory_model_ahb3lite.sv", line 153.
$finish at simulation time 0
make[2]: Leaving directory '/home/lightai/RISCV/RV12/sim/ahb3lite/regression/run/vcs'
make[1]: Leaving directory '/home/lightai/RISCV/RV12/sim/ahb3lite/regression/run'
make vcs LOG=./log/DCACHE_SIZE0@ICACHE_SIZE0@MEM_LATENCY0@WRITEBUFFER_SIZE0@XLEN64@rv64ui-p-addi.log \
PARAMS="DCACHE_SIZE=0 \
ICACHE_SIZE=0 \
MEM_LATENCY=0 \
WRITEBUFFER_SIZE=0 \
XLEN=64 \
MULT_LATENCY=rv64ui-p-addi \
HAS_U=1 HAS_S= HAS_H= \
HAS_RVA= HAS_RVC=0 HAS_RVM=1 \
TECHNOLOGY=GENERIC \
INIT_FILE=\"../../../../../bench/tests/regression/rv64ui-p-addi.hex\" "
make[1]: Entering directory '/home/lightai/RISCV/RV12/sim/ahb3lite/regression/run'
make[2]: Entering directory '/home/lightai/RISCV/RV12/sim/ahb3lite/regression/run/vcs'
Warning-[LCA_FEATURES_ENABLED] Usage warning
LCA features enabled by '-lca' argument on the command line. For more
information regarding list of LCA features please refer to Chapter "LCA
features" in the VCS/VCS-MX Release Notes
looks like the INIT_FILE has not been initialized into testbench, need help on this.
can't run the simulation with vcs, the command is only: "make SIM=vcs", guess the command is this the log is like this:
RISC-V Regression Testbench ----------- `---' ---------- XLEN | PRIV | MMU | FPU | RVA | RVM | MULLAT | CORES
64 | M SU | 0 | 0 | 0 | 0 | 0 | 1
Test = test.hex ICache = 0kB DCache = 0kB
Warning-[STASKW_CO] Cannot open file /home/lightai/RISCV/RV12/bench/verilog/ahb3lite/memory_model_ahb3lite.sv, 149 The file 'test.hex' could not be opened. No such file or directory. Please ensure that the file exists with proper permissions.
ERROR : Skip reading file test.hex. Reason file not found $finish called from file "/home/lightai/RISCV/RV12/bench/verilog/ahb3lite/memory_model_ahb3lite.sv", line 153. $finish at simulation time 0 make[2]: Leaving directory '/home/lightai/RISCV/RV12/sim/ahb3lite/regression/run/vcs' make[1]: Leaving directory '/home/lightai/RISCV/RV12/sim/ahb3lite/regression/run' make vcs LOG=./log/DCACHE_SIZE0@ICACHE_SIZE0@MEM_LATENCY0@WRITEBUFFER_SIZE0@XLEN64@rv64ui-p-addi.log \ PARAMS="DCACHE_SIZE=0 \ ICACHE_SIZE=0 \ MEM_LATENCY=0 \ WRITEBUFFER_SIZE=0 \ XLEN=64 \ MULT_LATENCY=rv64ui-p-addi \ HAS_U=1 HAS_S= HAS_H= \ HAS_RVA= HAS_RVC=0 HAS_RVM=1 \ TECHNOLOGY=GENERIC \ INIT_FILE=\"../../../../../bench/tests/regression/rv64ui-p-addi.hex\" " make[1]: Entering directory '/home/lightai/RISCV/RV12/sim/ahb3lite/regression/run' make[2]: Entering directory '/home/lightai/RISCV/RV12/sim/ahb3lite/regression/run/vcs'
Warning-[LCA_FEATURES_ENABLED] Usage warning LCA features enabled by '-lca' argument on the command line. For more information regarding list of LCA features please refer to Chapter "LCA features" in the VCS/VCS-MX Release Notes
looks like the INIT_FILE has not been initialized into testbench, need help on this.