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RoaLogic / RV12

RISC-V CPU Core
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Synth Error: Illegal biu_size_t #23

Open jeppojeps opened 5 years ago

jeppojeps commented 5 years ago

Hello, I am trying to synthesize the core but I get the above error, I am using Xilinx Vivado and my board is a Artyx 7 I am quite new to this.

jeppojeps commented 5 years ago

I have reverted commit e511751aec350be040fcbf0de2d56adea39708c1 and it worked, any ideas?

rherveille commented 2 years ago

Please try the latest dev branch