RoaLogic / RV12

RISC-V CPU Core
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Debug Control #28

Open abdallah250 opened 3 years ago

abdallah250 commented 3 years ago

Did you implement the DAP [ Debug Access Port ] what is protocol compatible with your debug control : SWD or JTAG ?

rherveille commented 2 years ago

Not yet. The CPU subsystem uses the RoaLogic JTAG TAP and adv_dbg_system. Together with the associated OpenOCD port. OpenOCD + GDB is supported.