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RoaLogic / RV12

RISC-V CPU Core
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Documents Update #9

Closed riscveval closed 6 years ago

riscveval commented 6 years ago

Hi The Documents links are unable to open. So can you update Documents? also also update the Makefile targets?

rherveille commented 6 years ago

1) The documentation is not yet in a state where we can release it. We are working on it. As soon as it's ready and reviewed we'll release it. We will add a note ... 2) What updates to the makefile targets would you like?

riscveval commented 6 years ago

How to run benchmarks and simulation ? also any FPGA design flow for RV12?

rherveille commented 6 years ago

To run the regression tests go to sim/ahb3lite/regression/run Do "make SIM=" to start the regression test, where simulator is one of msim, riviera, vcs, ncsim. For ModelSim, Riviera-PRO, VCS, and ncsim respectively.

sphardy commented 6 years ago

Hello @riscveval! I have been compiling documentation for all the Roa Logic IP including the RV12. A first draft for the other IP is now released in their Master branches.

For RV12, we are close to release but still need to complete one chapter. If you would like to take a look at what we currently have you can find it in the "Documentation" branch

PDF and markdown versions of the Datasheet are included in the branch. The README file provides links. The chapter we still need to complete is Chapter 3 - RV12 Execution Pipeline.

If you could provide feedback that would be very helpful. Please open new issues for what you find.

sphardy commented 6 years ago

Documentation is now formally released

Closing this issue