I believe there may be an issue with PADDR incrementing incorrectly. I'm using the ahb3lite_apb_bridge with a single instance of apb4_gpio directly connected. the AHB3 bus is 32-bit data/address while the APB bus is only 8-bit address/data. When performing byte wise accesses from the CPU everything works as expected. However when trying 32 bit accessing via the bridge I see PADDR increment by 4 (per beat) due to:
line 498: PADDR <= PADDR + (1 << ahb_hsize);
I believe this should be:
line 498: PADDR <= PADDR + (PDATA_SIZE/8);
With this change word and hword accesses appear to work as expected.
Cheers,
rherveille
commented
4 years ago
Hi @rherveille,
I believe there may be an issue with PADDR incrementing incorrectly. I'm using the ahb3lite_apb_bridge with a single instance of apb4_gpio directly connected. the AHB3 bus is 32-bit data/address while the APB bus is only 8-bit address/data. When performing byte wise accesses from the CPU everything works as expected. However when trying 32 bit accessing via the bridge I see PADDR increment by 4 (per beat) due to: line 498: PADDR <= PADDR + (1 << ahb_hsize); I believe this should be: line 498: PADDR <= PADDR + (PDATA_SIZE/8);
With this change word and hword accesses appear to work as expected. Cheers,