issues
search
RoaLogic
/
plic
Platform Level Interrupt Controller
Other
34
stars
14
forks
source link
issues
Newest
Newest
Most commented
Recently updated
Oldest
Least commented
Least recently updated
PRIORITIES value less than 3 and greater than 0 is generating a compile time error
#15
hassanraza-10x
opened
1 year ago
0
Can PLIC ensure that the ID read by targets other than the first is 0
#14
spzeno
opened
1 year ago
0
ID
#13
spzeno
closed
1 year ago
0
PRIORITY and THRESHOLD
#12
spzeno
closed
1 year ago
2
Icarus Verilog Support;
#11
PedroAntunes178
closed
1 year ago
1
Design Compiler Synthesis Error
#10
cr8601
opened
3 years ago
2
Broken Link to the RISC-V Privilege Level
#9
CLappin
opened
3 years ago
3
address2register return out of range register index when PLIC base address is not 0x0
#8
Elie1968
opened
4 years ago
0
PLIC Formatting Update
#7
sphardy
closed
6 years ago
0
Initial Documentation Release
#6
sphardy
closed
6 years ago
0
Initial Documentation Review
#5
rherveille
closed
6 years ago
0
Documentation review
#4
rherveille
closed
6 years ago
0
Documentation review
#3
rherveille
closed
6 years ago
0
Documentation Feedback from Richard
#2
sphardy
closed
6 years ago
1
Documentation
#1
sphardy
closed
7 years ago
0