Rutherther / vhdl-i2c

I2C master and slave implementation in VHDL
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Add possibility to override bus busy without full reset? #7

Open Rutherther opened 10 months ago

Rutherther commented 10 months ago

Add a signal telling to reset the internal state only, nothing else. That will ensure that the design can reliably reset without losing any data etc. Only the top design knows how many masters there should be etc., and thus if it's possible for something else to be keeping the bus