Fish-Git commented 4 years ago

NOTE: This issue has been closed and is now being continued in a NEW GitHub issue, #339: "Transactional-Execution Facility... (continued) "

I have been told the recently released z/OS 2.4 requires the availability of both the Transactional-Execution Facility and Constrained-Transactional-Execution Facility in order to successfully IPL:

Transactional-Execution enforcement

z/OS V2.4 provides enforcement to the effect that hardware Transactional-Execution, available on IBM Z servers since zEC12, is always available to programs running on z/OS V2.4 so that programs in such an environment can unconditionally assume and make use of Transactional-Execution.

https://www-01.ibm.com/common/ssi/ShowDoc.wss?docURL=/common/ssi/rep_ca/0/877/ENUSZP19-0410/index.html

This GitHub Issue is being created so that we can, together, discuss how best to implement this facility. Please offer your suggested approach/design as a GitHub comment reply to this issue.

I myself have a vague idea of how maybe it might be implemented, but I don't know if it will even fly nor especially how good it is. It's entirely possible (even likely!) that one of you might be able to come up with a better idea. (Please?)

Besides the description of the facility in the Principles of Operation manual, here are some additional papers I found on the subject to help get your creative juices flowing:

Transactional-Execution Facility.zip

I've also assigned everyone to this issue because I really, really want everyone to contribute with their own thoughts/ideas on how is the best way to implement this facility in Hercules.

Thanks!

_NOTE: This issue should be considered a specific sub-issue of issue #77 "MISSING Facilities support".__

EDIT: The following items still remain to be done:

(Feel free to add additional items as needed)

[ ] FORMAL TESTING! We still need a comprehensive set of tests (preferably standalone runtests) to verify proper functionality of all aspects of TXF! Right now we're simply using z/OS and z/VM and just presuming it's working correctly as long as both operating systems appear to function "normally", but of course that is not good enough!
[x] 'txf' tracing
[x] #define DEBUG tracing (TRACE macro)
[x] PTT tracing (PTT_TXF ==> PTT( PTT_CL_TXF ...)
[x] Constrained transactions constraint: 2. "All instructions in the transaction must be within 256 contiguous bytes of storage, including the TRANSACTION BEGIN (TBEGINC) and any TRANSACTION END instructions." (page 5-107)
[x] Constrained transactions constraint: 4. "The transaction’s storage operands access no more than four octowords. Note: LOAD ON CONDITION and STORE ON CONDITION are considered to reference storage regardless of the condition code." (page 5-109)
[ ] Constrained transactions constraint: 5. "The transaction executing on this CPU, or stores by other CPUs or the channel subsystem, do not access storage operands in any 4 K-byte blocks that contain the 256 bytes of storage beginning with the TRANSACTION BEGIN (TBEGINC) instruction." (page 5-109)
[ ] Constrained transactions constraint: 7. "Operand references made by each instruction in the transaction must be within a single double-word, except that for LOAD ACCESS MULTIPLE, LOAD MULTIPLE, LOAD MULTIPLE HIGH, STORE ACCESS MULTIPLE, STORE MULTIPLE, and STORE MULTIPLE HIGH, operand references must be within a single octoword." (page 5-109)
[ ] PER as it relates to TXF. (pages 4-26++, 5-89++)
[x] SIE as it relates to TXF. (Refer to GitHub Issue Comment below for some details)
[x] FPCR update on abort: "In addition to the diagnostic information saved in the TDB, when a transaction is aborted due to any data-exception program-exception condition and both the AFP-register control, bit 45 of control register 0, and the effective allow-floating-point-operation control (F) are one, the data-exception code (DXC) is placed into byte 2 of the floating-point control register (FPCR), regardless of whether filtering applies to the program-interruption condition." (page 5-97)

Note that constraints #4 and #7 seem to contradict one another. One says four octowords (4x32=128 bytes) whereas the other says a single double-word (8 bytes). Unless #4 means four octowords in total?? Constraint 5 is going to be next to impossible. Not sure about 7.

Peter-J-Jansen commented 4 years ago

Well that was bound to happen sooner or later (ok, 7 years later).

Presuming z/OS 2.4 will be able to run under z/VM (7.1?), will SIE have to support these instructions?

Cheers,

Peter

rwoodpd commented 4 years ago

z/VM 6.4 and above support z/OS 2.4, so I am sure that SIE will need to support it.

ivan-w commented 4 years ago

I don't think there is any issue with SIE supporting it.

The issue is supporting TXF as a whole.

Remember you are not only making a transaction on registers but also on any storage change, and those need to be capable of being rolled back or committed, and the entire transaction needs to be viewed as atomic by all the other entities (CPUs and Channel). This requires implementing some form of storage modification journal/log. It's possible a COW mechanism might be sufficient.

And then of course you need to except/intercept all the instructions that can't be used within a Transaction (a lot of them and some depending on how they are specified.. For example a backward branch is a no-no - no loops are allowed in a transaction).

Fish-Git commented 4 years ago

For example a backward branch is a no-no - no loops are allowed in a transaction

That's only for constrained transactions, not unconstrained. They're also only allowed to execute at most a total of 32 instructions too, all of which must be within the same 256-byte contiguous area of storage.

Unconstrained transactions do not have such limitations. They can execute as many contiguous or non-contiguous instructions as they want and loop all they want, branching to anywhere they want (forward or backward). Their only restriction is branch and/or mode tracing isn't enabled.

It's possible a COW mechanism might be sufficient.

What's "COW"?

As for me, I'm still tossing around some type of "shadow" storage key array approach that tracks which pages a transaction stores into (along with a copy of the page that can later be committed or discarded as appropriate), but the devil of course is in the details.

rwoodpd commented 4 years ago

COW = Copy on Write. Not sure if that would work for this. I think we need to queue the storage updates and actually write to storage on commit. We also will need to remember the location of a TBEGIN instruction in case of abort, which will happen if something else updates the storage before the commit (for an unconstrained transaction). I think some type of table pointed to the REGS structure may be in order. There is a CPU based limit on the number of stores that can be tracked. An abort also happens if that limit is exceeded.

s390guy commented 4 years ago

On Wed, 2019-10-23 at 23:40 -0700, rwoodpd wrote:

COW = Copy on Write. not sure if that would work for this. I think we need to queue the storage updates and actually write to storage on commit.

The semantics of Transactional-Execution Facility requires updates to storage to be seen by the program. The queue needs to be the original contents so that all of the storage changes can be reverted at one time. The reversion is essentially an atomic operation. This is clear from how this works at the level of the hardware CPU micro-code combined with the hardware interface to storage.

We also will need to remember the location of a TBEGIN instruction in case of abort, which will happen if something else updates the storage before the commit (for an unconstrained transaction). I think some type of table pointed to the REGS structure may be in order.

Some things are CPU specific. For those certainly, changes to the REGS structure may be appropriate. Some things are not.

There is a CPU based limit on the number of stores that can be tracked. An abort also happens if that limit is exceeded.

This is true. However the storage changes that are tracked are global in nature. Changes to storage by I/O can cause a transaction to abort.

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Fish-Git commented 4 years ago

@s390guy

FYI: https://github.com/SDL-Hercules-390/hyperion/issues/203#issuecomment-488819595

Peter-J-Jansen commented 4 years ago

If I understand things correctly, then the granularity of the transactional store conflicts on the real iron is a 'cache line', which I think today is 256 bytes (contiguous, aligned). Hercules has currently no such concept, but I presume we'd have to implement something similar. The number of such cache lines to provide for transactional execution could be a new Hercules config parameter.

All global storage access will need to check whether the same cache line is already marked as a 'transactional store is in progress'. Seems like an unavoidable overhead. Which makes me believe that this Transactional-Execution feature is only going to slow things down when only a few CPU's are available.

For the non-constraint TBEGIN instruction therefore a simple emulation could be to just always return CC=3, as all such transactions must be able to cope with that. But for the constraint TBEGINC I see no such 'poor-man' emulation possibility.

Well, this is not going to be easy.

Anyone having a z/OS 2.4 to test yet ?

Cheers,

Peter

rwoodpd commented 4 years ago

I am testing on a 2.4 system. It works by just setting the 50 and 73 bits for the STFLE instruction if only one CPU is configured.

It looks like z/OS makes heavy use of TBEGINC, but not TBEGIN.

I was able to get z/OS to come up correctly by adding a new lock for TBEGINC (similar to the mainlock). The lock is obtained at TBEGINC and released if an interrupt occurs, or when TEND is issued. That in effect serialized the transaction. Without the lock, all types of weird abends start occurring once all CPUS are online (I am testing with 4). With the lock, there are no issues.

Since a constrained transaction is limited to 32 instructions, that may be a valid way to process constrained transactions. For non-constrained, I think there is no choice but to have a tracking table that keeps track of stores and fetches when in transaction mode. The table would need to be checked for all main storage fetches and stores if any CPUs were in transactional mode. Code will also need to be added to the interrupt routines. Fortunately, there is a limit to the number of stores and fetches that can be tracked. The limit could be a parameter.

Bob Wood

Peter-J-Jansen commented 4 years ago

Interesting Bob!

The mainlock-style (but different) lock thus works, but am I correct to assume that this only works with one CPU configured?

In order to make this 'poor-man TBEGINC' work for multiple CPU's, the lock being held by any CPU would need to imply that all other CPU's would need to stop executing instructions until that lock is released. Thus all other CPU's would need to inspect that TBEGINC lock prior to each instruction, which is why I discarded the idea. But perhaps this could work.

As I said before, a 'poor-man TBEGIN' (i.e. non-constrained) could simply always return a CC=3 condition I think. Could you perhaps try that as well?

Cheers,

Peter

Peter-J-Jansen commented 4 years ago

I read Bob's last comment again and saw that this TBEGINC lock also works with 4 CPU's, without the extra checking by CPU's not holding the TBEGINC lock. That makes sense for well behaving TBEGINC software, but in principle (no pun intended) it would be possible for a CPU not in transaction mode to access storage that is used while another CPU is in TBEGINC mode. And in that case the TBEGINC would need to (automatically) backout and retry, right? Such backout and retry can be avoided if the TBEGINC lock could guarantee that all other CPU's wait until the max. 32 TBEGINC instructions are finished and the TBEGINC lock released. Or am I wrong?

Cheers,

Peter

rwoodpd commented 4 years ago

Right

Bob

dasdman commented 4 years ago

I would strongly suggest re-reading the principles regarding the interactions; it does not operate as suggested between CPUs unless the CPUs are referencing the same lock. In addition, the current mainlock is over utilized on systems supporting atomic operations.

Mark

rwoodpd commented 4 years ago

The CPUS are sharing the same lock. It may well not be a good long term solution, but it does allow z/OS to come up without errors.

Bob

Fish-Git commented 4 years ago

I would strongly suggest re-reading the principles regarding the interactions; it does not operate as suggested between CPUs unless the CPUs are referencing the same lock. In addition, the current mainlock is over utilized on systems supporting atomic operations.

Wiser words have never been spoken. Everyone needs to thoroughly read and re-read and re-read again (and again and again) pages 5-89 through 5-109 of the Principles of Operation which describes the Transactional-Execution Facility. Using a lock the way Bob suggested is simply not going to work. It's a no-go from the get-go.

Fish-Git commented 4 years ago

I believe the first step in this endeavor should probably be writing a test program to prove whatever implementation we eventually come up with is actually correct. This test program should test all aspects of the facility and be able to reliably detect incorrect functionality (architectural violations).

Having such a program beforehand is IMHO critical to the overall success of this project. Afterall, it hardly matters whether we have an implementation which we believe is correct if we're unable to actually prove that it is!

Developing such a program beforehand would also help to identify easily overlooked details that a given implementation must reliably account for (be able to properly deal with). Such a program would likely have a strong impact (influence) on our eventual design too, as it would serve to identify its possible weaknesses and problem areas.

The point is, I strongly feel we should be thinking first about how to test the proper functioning of the facility (all architectural aspects of it), which in turn will help us to then determine the best way to go about actually implementing it.

And as always, correctness of functionality comes first and performance/efficiency (speed) comes second. Once we have an implementation that we know works, then we can worry about how to make it better (faster).

ivan-w commented 4 years ago

Step 1 - For implementation, first thing is to set a base so that TEND/TABORT/Filtered Program interrupts/Constraint can resume after TBEGIN/TBEGINC with the proper code (involves some setjmp/longjmp).

Will start working on this now.

rwoodpd commented 4 years ago

TBEGINC restarts at the TBEGINC instruction. Constraint violations cause an actual interrupt if in constrained mode. In non-constrained mode, control is given to the instruction following the TBEGIN with a non-zero condition code. I have verified that on real hardware. I have it working on my machine. I have everything working except for program interrupt filtering. A long jump is indeed needed for the abort condition.

ivan-w commented 4 years ago

Thanks for the clarification! Right now I'm starting to set up the framework for TXF/CTXFC. One step at a time! (Yes, I know there is no PIFC for TBEGINC since it doesn't have a TDB.)

ivan-w commented 4 years ago

And since a TBEGINC nested within a TBEGIN is a TBEGIN... (and as far as I understand only the 1st level TBEGIN TDB counts).

rwoodpd commented 4 years ago

That is true. As I said, I already have much of this coded.

ivan-w commented 4 years ago

Would you mind sharing whatever you have (clone/fork/branch)? It doesn't have to be in a working state!

rwoodpd commented 4 years ago

Would you mind sharing whatever you have (clone/fork/branch)? It doesn't have to be in a working state!

No problem. I will gather together the changed files and send them to you.

As far as the branching goes, when appropriate, a function called abort_transaction is called to handle abort. It restores the requested registers and sets the fields in the TDB (if applicable). It also sets the condition code in the PSW. When the transaction starts, the restart PSW is saved (instruction after the TBEGIN or the TBEGINC). The PSW in the REGS structure is replaced with the restart PSW. Then, for TBEGINC if the abort is due to a fetch or store conflict, the transaction is restarted, otherwise a program check occurs (program_interrupt is called).

For TBEGIN, the transaction is restarted at the instruction after TBEGIN, unless the abort is for an unfiltered program check. In that case, the program interrupt occurs. When a restart is done, a long jump progjmp. I did not see a need for another jump point. Otherwise, program_interrupt will store the current psw (the restart PSW), and then load the program interrupt new PSW as normal.

Fish-Git commented 4 years ago

Would you mind sharing whatever you have (clone/fork/branch)? It doesn't have to be in a working state!

No problem. I will gather together the changed files and send them to you.

I too am very interested in seeing your implementation! (just as I'm sure the other developers are!)

Thanks!

rwoodpd commented 4 years ago

Attached is a zip file containing all of the source files I changed for the transaction execution facility, along with a text document describing the changes.    I welcome any comments, suggestions or questions.   This is still a work in progress,.  I might also note that while I think this code will be functionally correct, it would be nearly impossible to do a parallel test with real hardware since parallelism is involved and so there are timing issues.  Also, the principles of operations is not precise on some of the details, such as the number of separate updates that need to occur before a fetch or store overflow is detected.   I did some testing on a z14, and the number there was 64, so that is what I used.   I can say that z/OS 2.4 makes heavy use of constrained transactions, and my code supports that with no problem.   I have done some testing with unconstrained transactions, but nothing so far that will test simultaneous access.

From: Fish-Git notifications@github.com Sent: Thursday, December 5, 2019 5:15 PM To: SDL-Hercules-390/hyperion hyperion@noreply.github.com Cc: rwoodpd rwoodpd@gmail.com; Assign assign@noreply.github.com Subject: Re: [SDL-Hercules-390/hyperion] Transactional-Execution Facility design / implementation (#263)

Would you mind sharing whatever you have (clone/fork/branch)? It doesn't have to be in a working state!

No problem. I will gather together the changed files and send them to you.

I too am very interested in seeing your implementation! (just as I'm sure the other developers are!)

Thanks!

— You are receiving this because you were assigned. Reply to this email directly, view it on GitHub https://github.com/SDL-Hercules-390/hyperion/issues/263?email_source=notifications&email_token=AB655DFRP34BGPR3ILCVN6DQXGDOFA5CNFSM4JBAT3DKYY3PNVWWK3TUL52HS4DFVREXG43VMVBW63LNMVXHJKTDN5WW2ZLOORPWSZGOEGCPDVI#issuecomment-562360789 , or unsubscribe https://github.com/notifications/unsubscribe-auth/AB655DHL2LDCQCDGEMUZFELQXGDOFANCNFSM4JBAT3DA . https://github.com/notifications/beacon/AB655DDL3OZNJZ5CI6ZNBFDQXGDOFA5CNFSM4JBAT3DKYY3PNVWWK3TUL52HS4DFVREXG43VMVBW63LNMVXHJKTDN5WW2ZLOORPWSZGOEGCPDVI.gif

Fish-Git commented 4 years ago

@rwoodpd

Bob,

Attached is a zip file containing all of the source files I changed for the transaction execution facility, along with a text document describing the changes ...

Unfortunately there is no attachment. This is probably because you replied to GitHub via email instead of replying directly via the GitHub Issues web page itself (which is why I always recommend replying directly and not by email):

(I know you're not the same Bob as in the above examples but the comments still apply)

Notice at the bottom of the input box where you type in your github comment reply there is a dotted line and text below it which says: "Attach files by dragging & dropping, selecting or pasting them.".

"File attachments on issues and pull requests"

Thanks!

rwoodpd commented 4 years ago

Here is the attachment:

herctran.zip

Fish-Git commented 4 years ago

Here is the attachment:

Thanks!

I've only begun examining it and it's obviously going to take me quite some time to complete my review (many days more than likely, possibly weeks) but I've already discovered two small problems with it:

It doesn't compile! :) It gets an error in inline.h for PGM_TRANSACTION_CONSTRAINT_EXCEPTION being undefined.
It's missing enablement of the two facilities in facility.c.

Here's the fix:

diff -r -a -x .git -x 'msvc.AMD64.*' -x 'msvc.dllmod.*' -x 'msvc.debug.*' -x '*.suo' -x '*.ncb' -x '*.user' -x '*.htm' -x WORK -x DICTS -x FILES -x 'allTests.*' -x '*.rej' -x '*.orig' -x AutoBuildCount.h -x '*.cmp*' -x '*.comp*' -Nu hyperion-1/esa390.h hyperion-0/esa390.h
--- hyperion-1/esa390.h 2019-08-03 15:41:15.028513200 -0700
+++ hyperion-0/esa390.h 2019-12-17 20:24:16.940336400 -0800
@@ -1114,6 +1114,7 @@
 #define PGM_MONITOR_EVENT                               0x0040
 #define PGM_PER_EVENT                                   0x0080
 #define PGM_CRYPTO_OPERATION_EXCEPTION                  0x0119
+#define PGM_TRANSACTION_CONSTRAINT_EXCEPTION            0x0218

 /*-------------------------------------------------------------------*/
 /* External interrupt codes */
diff -r -a -x .git -x 'msvc.AMD64.*' -x 'msvc.dllmod.*' -x 'msvc.debug.*' -x '*.suo' -x '*.ncb' -x '*.user' -x '*.htm' -x WORK -x DICTS -x FILES -x 'allTests.*' -x '*.rej' -x '*.orig' -x AutoBuildCount.h -x '*.cmp*' -x '*.comp*' -Nu hyperion-1/facility.c hyperion-0/facility.c
--- hyperion-1/facility.c   2019-08-03 15:41:15.028513200 -0700
+++ hyperion-0/facility.c   2019-12-17 20:46:42.887853900 -0800
@@ -384,7 +384,7 @@
 /*-------------------------------------------------------------------*/

 #if defined(  FEATURE_050_CONSTR_TRANSACT_FACILITY )
-FT( NONE, NONE, NONE, 050_CONSTR_TRANSACT )
+FT( Z900, NONE, NONE, 050_CONSTR_TRANSACT )
 #endif

 #if defined(  FEATURE_051_LOCAL_TLB_CLEARING_FACILITY )
@@ -438,7 +438,7 @@
 #endif

 #if defined(  FEATURE_073_TRANSACT_EXEC_FACILITY )
-FT( NONE, NONE, NONE, 073_TRANSACT_EXEC )
+FT( Z900, NONE, NONE, 073_TRANSACT_EXEC )
 #endif

 #if defined(  FEATURE_074_STORE_HYPER_INFO_FACILITY )
@@ -2737,7 +2737,7 @@
     DIS_FAC_INS( B2EC, "ETND    B2EC  EXTRACT TRANSACTION NESTING DEPTH" );
     DIS_FAC_INS( E325, "NTSTG   E325  NONTRANSACTIONAL STORE (64)" );
     DIS_FAC_INS( B2FC, "TABORT  B2FC  TRANSACTION ABORT" );
-    DIS_FAC_INS( E560, "TBEGIN  E560  TRANSACTION BEGIN (nonconstrained)" );
+    DIS_FAC_INS( E560, "TBEGIN  E560  TRANSACTION BEGIN (unconstrained)" );
     DIS_FAC_INS( B2F8, "TEND    B2F8  TRANSACTION END" );
 }
 END_DIS_FAC_INS_FUNC()

More later as I continue my review ...

Thank you for your effort, Bob! Much appreciated my friend! It's a big step forward! Now we at least have something we can sink our teeth into! :)

rwoodpd commented 4 years ago

It compiles on my system using VS 2017. It looks like I missed including esa390.h and facility.c

Bob

From: Fish-Git notifications@github.com Sent: Tuesday, December 17, 2019 11:00 PM To: SDL-Hercules-390/hyperion hyperion@noreply.github.com Cc: rwoodpd rwoodpd@gmail.com; Mention mention@noreply.github.com Subject: Re: [SDL-Hercules-390/hyperion] Transactional-Execution Facility design / implementation (#263)

Here is the attachment:

Thanks!

I've only begun examining it and it's obviously going to take me quite some time to complete my review (many days more than likely, possibly weeks) but I've already discovered two small problems with it:

It doesn't compile! :) It gets an error in inline.h for PGM_TRANSACTION_CONSTRAINT_EXCEPTION being undefined.
It's missing enablement of the two facilities in facility.c.

Here's the fix:

diff -r -a -x .git -x 'msvc.AMD64.' -x 'msvc.dllmod.' -x 'msvc.debug.' -x '.suo' -x '.ncb' -x '.user' -x '.htm' -x WORK -x DICTS -x FILES -x 'allTests.' -x '.rej' -x '.orig' -x AutoBuildCount.h -x '.cmp' -x '.comp' -Nu hyperion-1/esa390.h hyperion-0/esa390.h

--- hyperion-1/esa390.h 2019-08-03 15:41:15.028513200 -0700

+++ hyperion-0/esa390.h 2019-12-17 20:24:16.940336400 -0800

@@ -1114,6 +1114,7 @@

define PGM_MONITOR_EVENT 0x0040

define PGM_PER_EVENT 0x0080

define PGM_CRYPTO_OPERATION_EXCEPTION 0x0119

+#define PGM_TRANSACTION_CONSTRAINT_EXCEPTION 0x0218

/-------------------------------------------------------------------/

/ External interrupt codes /

diff -r -a -x .git -x 'msvc.AMD64.' -x 'msvc.dllmod.' -x 'msvc.debug.' -x '.suo' -x '.ncb' -x '.user' -x '.htm' -x WORK -x DICTS -x FILES -x 'allTests.' -x '.rej' -x '.orig' -x AutoBuildCount.h -x '.cmp' -x '.comp' -Nu hyperion-1/facility.c hyperion-0/facility.c

--- hyperion-1/facility.c 2019-08-03 15:41:15.028513200 -0700

+++ hyperion-0/facility.c 2019-12-17 20:46:42.887853900 -0800

@@ -384,7 +384,7 @@

/-------------------------------------------------------------------/

if defined( FEATURE_050_CONSTR_TRANSACT_FACILITY )

-FT( NONE, NONE, NONE, 050_CONSTR_TRANSACT )

+FT( Z900, NONE, NONE, 050_CONSTR_TRANSACT )

endif

if defined( FEATURE_051_LOCAL_TLB_CLEARING_FACILITY )

@@ -438,7 +438,7 @@

endif

if defined( FEATURE_073_TRANSACT_EXEC_FACILITY )

-FT( NONE, NONE, NONE, 073_TRANSACT_EXEC )

+FT( Z900, NONE, NONE, 073_TRANSACT_EXEC )

endif

if defined( FEATURE_074_STORE_HYPER_INFO_FACILITY )

@@ -2737,7 +2737,7 @@

 DIS_FAC_INS( B2EC, "ETND    B2EC  EXTRACT TRANSACTION NESTING DEPTH" );

 DIS_FAC_INS( E325, "NTSTG   E325  NONTRANSACTIONAL STORE (64)" );

 DIS_FAC_INS( B2FC, "TABORT  B2FC  TRANSACTION ABORT" );

DIS_FAC_INS( E560, "TBEGIN E560 TRANSACTION BEGIN (nonconstrained)" );
DIS_FAC_INS( E560, "TBEGIN E560 TRANSACTION BEGIN (unconstrained)" );

DIS_FAC_INS( B2F8, "TEND B2F8 TRANSACTION END" );

}

END_DIS_FAC_INS_FUNC()

More later as I continue my review ...

Thank you for your effort, Bob! Much appreciated my friend! It's a big step forward! Now we at least have something we can sink our teeth into!

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rwoodpd commented 4 years ago

Looks like I forgot to include my copy of esa390.h and facility,c . Will send tomorrow if you need them.

Fish-Git commented 4 years ago

Looks like I forgot to include my copy of esa390.h and facility,c . Will send tomorrow if you need them.

Yes please.

Add them to your .zip file and re-attach the new updated .zip file to your subsequent github comment/reply again so we can all be sure we have your complete set of changes.

Thanks!

rpinion commented 4 years ago

I configured one CPU and enabled bits 50 & 73. However, I got

11:54:35.728 00001AE8 HHC00809I Processor CP00: disabled wait state 0002000080000000 0000000000009064

Fish-Git commented 4 years ago

I configured one CPU and enabled bits 50 & 73. However, I got:
11:54:35.728 00001AE8 HHC00809I Processor CP00: disabled wait state 0002000080000000 0000000000009064

That's a rather piss poor problem report, Richard.

Config file? Log file? Etc...

Fish-Git commented 4 years ago

Well, it seems to work (with emphasis on "seems")...

Now comes the tough part: proving that it does. (Ref: my Oct 25 comment)

I'm still scratching my head over that one...

rpinion commented 4 years ago

I was only stating that I tried the procedure that another person had tried.

Richard Pinion rpinion@netscape.com

-----Original Message----- From: Fish-Git notifications@github.com To: SDL-Hercules-390/hyperion hyperion@noreply.github.com Cc: rpinion rpinion@netscape.com; Comment comment@noreply.github.com Sent: Wed, Dec 18, 2019 5:17 pm Subject: Re: [SDL-Hercules-390/hyperion] Transactional-Execution Facility design / implementation (#263)

I configured one CPU and enabled bits 50 & 73. However, I got:11:54:35.728 00001AE8 HHC00809I Processor CP00: disabled wait state 0002000080000000 0000000000009064

That's a rather piss poor problem report, Richard.Config file? Log file? Etc...— You are receiving this because you commented. Reply to this email directly, view it on GitHub, or unsubscribe. 11:53:05.509 **** HHC046I Acceptance of PGMPRDOS LICENSED setting verified 11:53:05.512 **** Program to be executed = D:/hercules/4.1/Hercules.exe 11:53:05.513 **** Control file to be used = D:/hercules/zos240.txt 11:53:05.517 Hercules started; process-id=00003224 11:53:05.550 00003224 HHC00100I Thread id 0000071c, prio 5, name 'impl_thread' started 11:53:05.550 00003224 HHC00100I Thread id 0000246c, prio 4, name 'logger_thread' started 11:53:05.550 00003224 HHC01413I Hercules version 4.1.0.9426-SDL-g42b533fa (4.1.0.9426) 11:53:05.550 00003224 HHC01414I (C) Copyright 1999-2018 by Roger Bowler, Jan Jaeger, and others 11:53:05.550 00003224 HHC01417I The SoftDevLabs version of Hercules 11:53:05.550 00003224 HHC01415I Build date: Nov 10 2018 at 10:39:02 11:53:05.550 00003224 HHC01417I Built with: Microsoft Visual Studio 2008 (MSVC 150030729 1) 11:53:05.550 00003224 HHC01417I Build type: Windows MSVC AMD64 host architecture build 11:53:05.550 00003224 HHC01417I Modes: S/370 ESA/390 z/Arch 11:53:05.550 00003224 HHC01417I Max CPU Engines: 64 11:53:05.550 00003224 HHC01417I Using shared libraries 11:53:05.550 00003224 HHC01417I Using Fish threads Threading Model 11:53:05.550 00003224 HHC01417I Using Error-Checking Mutex Locking Model 11:53:05.550 00003224 HHC01417I With Shared Devices support 11:53:05.550 00003224 HHC01417I With Dynamic loading support 11:53:05.550 00003224 HHC01417I With External GUI support 11:53:05.550 00003224 HHC01417I With Partial TCP keepalive support 11:53:05.550 00003224 HHC01417I With IPV6 support 11:53:05.550 00003224 HHC01417I With HTTP Server support 11:53:05.550 00003224 HHC01417I With sqrtl support 11:53:05.550 00003224 HHC01417I Without SIGABEND handler 11:53:05.550 00003224 HHC01417I With CCKD BZIP2 support 11:53:05.550 00003224 HHC01417I With HET BZIP2 support 11:53:05.550 00003224 HHC01417I With ZLIB support 11:53:05.550 00003224 HHC01417I With Regular Expressions support 11:53:05.550 00003224 HHC01417I With Object REXX support 11:53:05.550 00003224 HHC01417I Without Regina REXX support 11:53:05.550 00003224 HHC01417I With Automatic Operator support 11:53:05.550 00003224 HHC01417I Without National Language Support 11:53:05.551 00003224 HHC01417I Machine dependent assists: cmpxchg1 cmpxchg4 cmpxchg8 hatomics=msvcIntrinsics 11:53:05.551 00003224 HHC01417I Running on: RPINION-PC (Windows-6.2.9200 Intel(R) x64) LP=8, Cores=4, CPUs=1 11:53:05.551 00003224 HHC01417I Built with decNumber external package version 3.68.0.79-g53f2512 11:53:05.551 00003224 HHC01417I Built with SoftFloat external package version 3.5.0.82-g1c66591 11:53:05.551 00003224 HHC01417I Built with telnet external package version 1.0.0.41-ged0ddec 11:53:05.551 00003224 HHC00018I Hercules is running in elevated mode 11:53:05.551 00003224 HHC02323W This build of Hercules has only partial TCP keepalive support 11:53:05.553 00003224 HHC00150I Crypto module loaded (C) Copyright 2003-2016 by Bernard van der Helm 11:53:05.553 00003224 HHC01417I Built with crypto external package version 1.0.0.26-gefe199e 11:53:05.553 00003224 HHC00151I Activated facility: Message Security Assist 11:53:05.553 00003224 HHC00151I Activated facility: Message Security Assist Extension 1, 2, 3 and 4 11:53:05.560 00003224 HHC17531W REXX(OORexx) dlopen 'rexx.dll' failed: The specified module could not be found. 11:53:05.560 00003224 HHC17511E REXX() Could not enable either Rexx package 11:53:05.560 00003224 HHC17511E REXX() Could not enable default Rexx package 11:53:05.560 00003224 HHC17500I REXX() Mode : Command 11:53:05.560 00003224 HHC17500I REXX() MsgLevel : Off 11:53:05.560 00003224 HHC17500I REXX() MsgPrefix : Off 11:53:05.560 00003224 HHC17500I REXX() ErrPrefix : Off 11:53:05.560 00003224 HHC17500I REXX() Resolver : On 11:53:05.560 00003224 HHC17500I REXX() SysPath (24) : On 11:53:05.560 00003224 HHC17500I REXX() RexxPath ( 0) : 11:53:05.560 00003224 HHC17500I REXX() Extensions ( 8) : .REXX;.rexx;.REX;.rex;.CMD;.cmd;.RX;.rx 11:53:05.562 00003224 HHC00111I Thread CPU Time IS available (_POSIX_THREAD_CPUTIME=1) 11:53:05.563 00003224 HHC00100I Thread id 000018f0, prio 7, name 'timer_thread' started 11:53:05.564 00003224 HHC00100I Thread id 00001c90, prio 2, name 'Processor CP00' started 11:53:05.564 00003224 HHC00811I Processor CP00: architecture mode z/Arch 11:53:05.564 00003224 HHC00898I Facility( 006_ASN_LX_REUSE ) Enabled for z/Arch 11:53:05.564 00003224 HHC00898W Facility( 044_PFPO ) *Enabled for z/Arch 11:53:05.564 00003224 HHC02204I MAXCPU set to 1 11:53:05.564 00003224 HHC00827I Processor CP00: engine 00 type 0 set: CP 11:53:05.564 00003224 HHC02204I NUMCPU set to 1 11:53:05.564 00003224 HHC02204I NUMVEC set to 1 11:53:05.564 00003224 HHC02256W Command 'HERCPRIO' is deprecated and ignored. 11:53:05.564 00003224 HHC02256W Command 'TODPRIO' is deprecated and ignored. 11:53:05.564 00003224 HHC02256W Command 'DEVPRIO' is deprecated and ignored. 11:53:05.564 00003224 HHC02256W Command 'CPUPRIO' is deprecated and ignored. 11:53:05.564 00003224 HHC02204I AUTO_SCSI_MOUNT set to NO 11:53:05.564 00003224 HHC02323W This build of Hercules has only partial TCP keepalive support 11:53:05.564 00003224 HHC02204I conkpalv set to (3,1,10) 11:53:05.564 00003224 HHC01474I Using internal codepage conversion table default 11:53:05.564 00003224 HHC02204I CPUMODEL set to 2098 11:53:05.564 00003224 HHC02204I CPUSERIAL set to 0E45A4 11:53:05.564 00003224 HHC02204I CPUVERID set to 00 11:53:05.564 00003224 HHC02204I DIAG8CMD set to DISABLE NOECHO 11:53:05.564 00003224 HHC02204I ECPSVM set to disabled 11:53:05.565 00003224 HHC01508I HDL: loadable module directory is 'D:/hercules/4.1' 11:53:05.565 00003224 HHC02204I MODPATH set to D:/hercules/4.1 11:53:05.565 00003224 HHC02204I LEGACYSENSEID set to disabled 11:53:05.565 00003224 HHC02204I LOADPARM set to 0AAACSM1 11:53:05.565 00003224 HHC02204I LPARNUM set to 01 11:53:05.565 00003224 HHC02204I LPARNAME set to HERCULES 11:53:05.578 00003224 HHC17003I MAIN storage is 6G (mainsize); storage is not locked 11:53:05.578 00003224 HHC02204I MANUFACTURER set to HRC 11:53:05.578 00003224 HHC02204I MODEL set to hardware(EMULATOR) capacity(EMULATOR) perm() temp() 11:53:05.578 00003224 HHC02204I MOUNTED_TAPE_REINIT set to enabled 11:53:05.578 00003224 HHC02204I PANRATE set to 50 11:53:05.578 00003224 HHC02204I PLANT set to ZZ 11:53:05.578 00003224 HHC02204I SHCMDOPT set to ENABLE NODIAG8 11:53:05.578 00003224 HHC02204I TIMERINT set to 50 11:53:05.578 00003224 HHC02204I TRACEOPT set to TRADITIONAL 11:53:05.578 00003224 HHC02204I TZOFFSET set to -0000 11:53:05.578 00003224 HHC17003I EXPANDED storage is 0 (xpndsize); storage is not locked 11:53:05.578 00003224 HHC02204I YROFFSET set to 0 11:53:05.579 00003224 HHC00100I Thread id 0000293c, prio 4, name 'console_connect' started 11:53:05.580 00003224 HHC01024I Waiting for console connections on port 3271 11:53:05.580 00003224 HHC00414I 0:0D02 CKD file H:/HerculesDasdFiles/LDAV01: cyls 3339 heads 15 tracks 50085 trklen 56832 11:53:05.580 00003224 HHC00414I 0:0D03 CKD file H:/HerculesDasdFiles/CFG001: cyls 20000 heads 15 tracks 300000 trklen 56832 11:53:05.580 00003224 HHC00414I 0:0A94 CKD file H:/HerculesDasdFiles/SPL001: cyls 3339 heads 15 tracks 50085 trklen 56832 11:53:05.593 00003224 HHC00414I 0:0A95 CKD file H:/HerculesDasdFiles/SPOOL2: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.594 00003224 HHC00414I 0:0A96 CKD file H:/HerculesDasdFiles/LDAV04: cyls 3339 heads 15 tracks 50085 trklen 56832 11:53:05.601 00003224 HHC00414I 0:0A9A CKD file H:/HerculesDasdFiles/LDAV07: cyls 3339 heads 15 tracks 50085 trklen 56832 11:53:05.608 00003224 HHC00414I 0:0A9B CKD file H:/HerculesDasdFiles/LDAV08: cyls 3339 heads 15 tracks 50085 trklen 56832 11:53:05.615 00003224 HHC00414I 0:0A9D CKD file H:/HerculesDasdFiles/JAIMS1: cyls 3339 heads 15 tracks 50085 trklen 56832 11:53:05.616 00003224 HHC00414I 0:0A9F CKD file H:/HerculesDasdFiles/LDAV05: cyls 3339 heads 15 tracks 50085 trklen 56832 11:53:05.616 00003224 HHC00414I 0:0D0A CKD file H:/HerculesDasdFiles/LDA023: cyls 32760 heads 15 tracks 491400 trklen 56832 11:53:05.671 00003224 HHC00414I 0:0D0B CKD file H:/HerculesDasdFiles/LDAV03: cyls 3339 heads 15 tracks 50085 trklen 56832 11:53:05.679 00003224 HHC00414I 0:0D11 CKD file H:/HerculesDasdFiles/LDA074: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.680 00003224 HHC00414I 0:0D12 CKD file T:/HerculesDasdFiles/LDA004: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.680 00003224 HHC00414I 0:0D13 CKD file T:/HerculesDasdFiles/LDA007: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.680 00003224 HHC00414I 0:0D14 CKD file T:/HerculesDasdFiles/LDA008: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.681 00003224 HHC00414I 0:0D15 CKD file T:/HerculesDasdFiles/LDA009: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.681 00003224 HHC00414I 0:0D16 CKD file T:/HerculesDasdFiles/LDA00A: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.681 00003224 HHC00414I 0:0A8A CKD file H:/HerculesDasdFiles/a3sys1: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.681 00003224 HHC00414I 0:0A8B CKD file H:/HerculesDasdFiles/a3cfg1: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.682 00003224 HHC00414I 0:0A8C CKD file H:/HerculesDasdFiles/a3dis1: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.682 00003224 HHC00414I 0:0A8D CKD file H:/HerculesDasdFiles/a3dis2: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.682 00003224 HHC00414I 0:0A8E CKD file H:/HerculesDasdFiles/a3dis3: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.683 00003224 HHC00414I 0:0A8F CKD file H:/HerculesDasdFiles/a3res1: cyls 30051 heads 15 tracks 450765 trklen 56832 11:53:05.683 00003224 HHC00414I 0:0A90 CKD file H:/HerculesDasdFiles/a3res2: cyls 30051 heads 15 tracks 450765 trklen 56832 11:53:05.683 00003224 HHC00414I 0:0AA0 CKD file H:/zos24/a4res2: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.684 00003224 HHC00414I 0:0AA1 CKD file H:/zos24/a4usr1: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.684 00003224 HHC00414I 0:0AA2 CKD file H:/zos24/a4uss1: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.684 00003224 HHC00414I 0:0AA3 CKD file H:/zos24/a4uss2: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.684 00003224 HHC00414I 0:0AA4 CKD file H:/zos24/a4cfg1: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.685 00003224 HHC00414I 0:0AA5 CKD file H:/zos24/a4dis1: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.685 00003224 HHC00414I 0:0AA6 CKD file H:/zos24/a4dis2: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.685 00003224 HHC00414I 0:0AA7 CKD file H:/zos24/a4dis3: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.685 00003224 HHC00414I 0:0AA8 CKD file H:/zos24/a4paga: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.686 00003224 HHC00414I 0:0AA9 CKD file H:/zos24/a4pagb: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.686 00003224 HHC00414I 0:0AAA CKD file H:/zos24/a4sys1: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.686 00003224 HHC00414I 0:0AAB CKD file H:/zos24/a4pagc: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.686 00003224 HHC00414I 0:0AAC CKD file H:/zos24/a4prd1: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.687 00003224 HHC00414I 0:0AAD CKD file H:/zos24/a4prd2: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.687 00003224 HHC00414I 0:0AAE CKD file H:/zos24/a4prd3: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.687 00003224 HHC00414I 0:0AAF CKD file H:/zos24/a4res1: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.687 00003224 HHC00414I 0:0AB0 CKD file H:/zos24/a4prd4: cyls 10017 heads 15 tracks 150255 trklen 56832 11:53:05.692 00003224 HHC00221I 0:0583 Tape file T:/herculesawstapefiles/000004.aws, type aws: format type AWS Format tape file 11:53:05.692 00003224 HHC00222I 0:0583 Tape file T:/herculesawstapefiles/000004.aws, type aws: option awstape accepted 11:53:05.692 00003224 HHC00222I 0:0583 Tape file T:/herculesawstapefiles/000004.aws, type aws: option maxsizeM accepted 11:53:05.693 00003224 HHC00222I 0:0583 Tape file T:/herculesawstapefiles/000004.aws, type aws: option eotmargin accepted 11:53:05.693 00003224 HHC00224I 0:0583 Tape file T:/herculesawstapefiles/000004.aws, type aws: display " NT RDY " 11:53:05.705 00003224 HHC04100I TunTap64.dll version 3.6.2.4906 initiated 11:53:05.982 00003224 HHC04100I TunTap64.dll version 3.6.2.4906 initiated 11:53:05.984 00003224 HHC00901I 0:0E20 LCS: Interface tap0, type TAP opened 11:53:05.984 00003224 HHC00921I CTC: lcs device port 00: tuntap Multicast assist enabled 11:53:05.984 00003224 HHC00935I CTC: lcs device port 00: manual Checksum Offload enabled 11:53:05.984 00003224 HHC01541I HDL: dyngui.dll initiated 11:53:17.608 00003224 HHC01603I loadparm 0AAACSM1 11:53:17.608 00003224 HHC02204I LOADPARM set to 0AAACSM1 11:53:17.859 00003224 HHC01603I ipl 0AAF 11:53:17.870 00003224 HHC00811I Processor CP00: architecture mode ESA/390 11:53:17.880 00003224 HHC00814I Processor CP00: SIGP Set architecture mode (12) CP00, PARM 00000001: CC 0 11:53:17.880 00003224 HHC00811I Processor CP00: architecture mode z/Arch 11:53:17.880 00003224 HHC00801I Processor CP00: Operation exception code 0001 ilc 2 11:53:17.880 00003224 HHC02324I PSW=0000000080000000 00000000000006D0 INST=0000 ????? , ? 11:53:17.880 00003224 HHC02269I R0=000000000021007B R1=0000000000000000 R2=0000000000000000 R3=0000000000000000 11:53:17.880 00003224 HHC02269I R4=0000000000000000 R5=0000000000000000 R6=0000000000000000 R7=0000000000000000 11:53:17.880 00003224 HHC02269I R8=0000000000000000 R9=0000000000000000 RA=0000000000000000 RB=0000000000000000 11:53:17.880 00003224 HHC02269I RC=0000000000000000 RD=0000000000000000 RE=0000000000000000 RF=0000000000000001 11:53:17.880 00003224 HHC00809I Processor CP00: disabled wait state 0002000080000000 000000000021007B 11:53:29.150 00003224 HHC01603I fcility enable 73 11:53:29.150 00003224 HHC01600E Unknown command fcility, enter 'help' for a list of valid commands 11:53:37.408 00003224 HHC01603I facility enable 73 11:53:37.408 00003224 HHC00889E Available facilities cannot be changed once system is IPLed 11:53:44.611 00003224 HHC01603I facility enable 50 11:53:44.611 00003224 HHC00889E Available facilities cannot be changed once system is IPLed 11:53:53.714 00003224 HHC01603I loadparm 0AAACSM1 11:53:53.714 00003224 HHC02204I LOADPARM set to 0AAACSM1 11:53:53.964 00003224 HHC01603I ipl 0AAF 11:53:53.975 00003224 HHC00811I Processor CP00: architecture mode ESA/390 11:53:53.986 00003224 HHC00814I Processor CP00: SIGP Set architecture mode (12) CP00, PARM 00000001: CC 0 11:53:53.986 00003224 HHC00811I Processor CP00: architecture mode z/Arch 11:53:53.986 00003224 HHC00801I Processor CP00: Operation exception code 0001 ilc 2 11:53:53.986 00003224 HHC02324I PSW=0000000080000000 00000000000006D0 INST=0000 ????? , ? 11:53:53.986 00003224 HHC02269I R0=000000000021007B R1=0000000000000000 R2=0000000000000000 R3=0000000000000000 11:53:53.986 00003224 HHC02269I R4=0000000000000000 R5=0000000000000000 R6=0000000000000000 R7=0000000000000000 11:53:53.986 00003224 HHC02269I R8=0000000000000000 R9=0000000000000000 RA=0000000000000000 RB=0000000000000000 11:53:53.986 00003224 HHC02269I RC=0000000000000000 RD=0000000000000000 RE=0000000000000000 RF=0000000000000001 11:53:53.986 00003224 HHC00809I Processor CP00: disabled wait state 0002000080000000 000000000021007B 11:54:09.494 00003224 HHC01603I stopall 11:54:13.237 00003224 HHC01603I exit 11:54:13.277 00003224 HHC01423I Calling termination routines 11:54:13.277 00003224 HHC00101I Thread id 00001c90, prio 2, name 'Processor CP00' ended 11:54:13.277 00003224 HHC00101I Thread id 0000293c, prio 4, name 'console_connect' ended 11:54:13.277 00003224 HHC00417I 0:0D02 CKD file H:/HerculesDasdFiles/LDAV01: cache hits 0, misses 0, waits 0 11:54:13.277 00003224 HHC00417I 0:0D03 CKD file H:/HerculesDasdFiles/CFG001: cache hits 0, misses 0, waits 0 11:54:13.277 00003224 HHC00333I 0:0A94 size free nbr st reads writes l2reads hits switches 11:54:13.277 00003224 HHC00335I 0:0A94 -------------------------------------------------------------------- 11:54:13.277 00003224 HHC00336I 0:0A94 [] 0024308761 004 % 0028 0000000 0000000 0000000 0000000 0000000 11:54:13.277 00003224 HHC00338I 0:0A94 H:/HerculesDasdFiles/SPL001 11:54:13.278 00003224 HHC00339I 0:0A94 [0] 0024308761 004 % 0028 rw 0000000 0000000 0000000 11:54:13.280 00003224 HHC00417I 0:0A95 CKD file H:/HerculesDasdFiles/SPOOL2: cache hits 0, misses 0, waits 0 11:54:13.280 00003224 HHC00333I 0:0A96 size free nbr st reads writes l2reads hits switches 11:54:13.280 00003224 HHC00335I 0:0A96 -------------------------------------------------------------------- 11:54:13.281 00003224 HHC00336I 0:0A96 [] 0553946411 000 % 0825 0000000 0000000 0000000 0000000 0000000 11:54:13.281 00003224 HHC00338I 0:0A96 H:/HerculesDasdFiles/LDAV04 11:54:13.281 00003224 HHC00339I 0:0A96 [0] 0553946411 000 % 0825 rw 0000000 0000000 0000000 11:54:13.283 00003224 HHC00333I 0:0A9A size free nbr st reads writes l2reads hits switches 11:54:13.283 00003224 HHC00335I 0:0A9A -------------------------------------------------------------------- 11:54:13.283 00003224 HHC00336I 0:0A9A [] 0679942946 000 % 0005 0000000 0000000 0000000 0000000 0000000 11:54:13.283 00003224 HHC00338I 0:0A9A H:/HerculesDasdFiles/LDAV07 11:54:13.283 00003224 HHC00339I 0:0A9A [0] 0679942946 000 % 0005 rw 0000000 0000000 0000000 11:54:13.285 00003224 HHC00333I 0:0A9B size free nbr st reads writes l2reads hits switches 11:54:13.286 00003224 HHC00335I 0:0A9B -------------------------------------------------------------------- 11:54:13.286 00003224 HHC00336I 0:0A9B [] 0223323353 000 % 0000 0000000 0000000 0000000 0000000 0000000 11:54:13.286 00003224 HHC00338I 0:0A9B H:/HerculesDasdFiles/LDAV08 11:54:13.286 00003224 HHC00339I 0:0A9B [0] 0223323353 000 % 0000 rw 0000000 0000000 0000000 11:54:13.288 00003224 HHC00417I 0:0A9D CKD file H:/HerculesDasdFiles/JAIMS1: cache hits 0, misses 0, waits 0 11:54:13.288 00003224 HHC00417I 0:0A9F CKD file H:/HerculesDasdFiles/LDAV05: cache hits 0, misses 0, waits 0 11:54:13.288 00003224 HHC00333I 0:0D0A size free nbr st reads writes l2reads hits switches 11:54:13.288 00003224 HHC00335I 0:0D0A -------------------------------------------------------------------- 11:54:13.288 00003224 HHC00336I 0:0D0A [] 1922033303 000 % 0072 0000000 0000000 0000000 0000000 0000000 11:54:13.288 00003224 HHC00338I 0:0D0A H:/HerculesDasdFiles/LDA023 11:54:13.288 00003224 HHC00339I 0:0D0A [0] 1922033303 000 % 0072 rw 0000000 0000000 0000000 11:54:13.290 00003224 HHC00333I 0:0D0B size free nbr st reads writes l2reads hits switches 11:54:13.290 00003224 HHC00335I 0:0D0B -------------------------------------------------------------------- 11:54:13.291 00003224 HHC00336I 0:0D0B [] 0208740369 000 % 0020 0000000 0000000 0000000 0000000 0000000 11:54:13.291 00003224 HHC00338I 0:0D0B H:/HerculesDasdFiles/LDAV03 11:54:13.291 00003224 HHC00339I 0:0D0B [0] 0208740369 000 % 0020 rw 0000000 0000000 0000000 11:54:13.293 00003224 HHC00333I 0:0D11 size free nbr st reads writes l2reads hits switches 11:54:13.293 00003224 HHC00335I 0:0D11 -------------------------------------------------------------------- 11:54:13.293 00003224 HHC00336I 0:0D11 [*] 0006682032 000 % 0000 0000000 0000000 0000000 0000000 0000000 11:54:13.293 00003224 HHC00338I 0:0D11 H:/HerculesDasdFiles/LDA074 11:54:13.293 00003224 HHC00339I 0:0D11 [0] 0006682032 000 % 0000 rw 0000000 0000000 0000000 11:54:13.296 00003224 HHC00417I 0:0D12 CKD file T:/HerculesDasdFiles/LDA004: cache hits 0, misses 0, waits 0 11:54:13.296 00003224 HHC00417I 0:0D13 CKD file T:/HerculesDasdFiles/LDA007: cache hits 0, misses 0, waits 0 11:54:13.296 00003224 HHC00417I 0:0D14 CKD file T:/HerculesDasdFiles/LDA008: cache hits 0, misses 0, waits 0 11:54:13.296 00003224 HHC00417I 0:0D15 CKD file T:/HerculesDasdFiles/LDA009: cache hits 0, misses 0, waits 0 11:54:13.296 00003224 HHC00417I 0:0D16 CKD file T:/HerculesDasdFiles/LDA00A: cache hits 0, misses 0, waits 0 11:54:13.296 00003224 HHC00417I 0:0A8A CKD file H:/HerculesDasdFiles/a3sys1: cache hits 0, misses 0, waits 0 11:54:13.296 00003224 HHC00417I 0:0A8B CKD file H:/HerculesDasdFiles/a3cfg1: cache hits 0, misses 0, waits 0 11:54:13.296 00003224 HHC00417I 0:0A8C CKD file H:/HerculesDasdFiles/a3dis1: cache hits 0, misses 0, waits 0 11:54:13.296 00003224 HHC00417I 0:0A8D CKD file H:/HerculesDasdFiles/a3dis2: cache hits 0, misses 0, waits 0 11:54:13.296 00003224 HHC00417I 0:0A8E CKD file H:/HerculesDasdFiles/a3dis3: cache hits 0, misses 0, waits 0 11:54:13.296 00003224 HHC00417I 0:0A8F CKD file H:/HerculesDasdFiles/a3res1: cache hits 0, misses 0, waits 0 11:54:13.296 00003224 HHC00417I 0:0A90 CKD file H:/HerculesDasdFiles/a3res2: cache hits 0, misses 0, waits 0 11:54:13.296 00003224 HHC00417I 0:0AA0 CKD file H:/zos24/a4res2: cache hits 0, misses 0, waits 0 11:54:13.296 00003224 HHC00417I 0:0AA1 CKD file H:/zos24/a4usr1: cache hits 0, misses 0, waits 0 11:54:13.296 00003224 HHC00417I 0:0AA2 CKD file H:/zos24/a4uss1: cache hits 0, misses 0, waits 0 11:54:13.296 00003224 HHC00417I 0:0AA3 CKD file H:/zos24/a4uss2: cache hits 0, misses 0, waits 0 11:54:13.297 00003224 HHC00417I 0:0AA4 CKD file H:/zos24/a4cfg1: cache hits 0, misses 0, waits 0 11:54:13.297 00003224 HHC00417I 0:0AA5 CKD file H:/zos24/a4dis1: cache hits 0, misses 0, waits 0 11:54:13.297 00003224 HHC00417I 0:0AA6 CKD file H:/zos24/a4dis2: cache hits 0, misses 0, waits 0 11:54:13.297 00003224 HHC00417I 0:0AA7 CKD file H:/zos24/a4dis3: cache hits 0, misses 0, waits 0 11:54:13.297 00003224 HHC00417I 0:0AA8 CKD file H:/zos24/a4paga: cache hits 0, misses 0, waits 0 11:54:13.297 00003224 HHC00417I 0:0AA9 CKD file H:/zos24/a4pagb: cache hits 0, misses 0, waits 0 11:54:13.297 00003224 HHC00417I 0:0AAA CKD file H:/zos24/a4sys1: cache hits 0, misses 0, waits 0 11:54:13.297 00003224 HHC00417I 0:0AAB CKD file H:/zos24/a4pagc: cache hits 0, misses 0, waits 0 11:54:13.297 00003224 HHC00417I 0:0AAC CKD file H:/zos24/a4prd1: cache hits 0, misses 0, waits 0 11:54:13.297 00003224 HHC00417I 0:0AAD CKD file H:/zos24/a4prd2: cache hits 0, misses 0, waits 0 11:54:13.297 00003224 HHC00417I 0:0AAE CKD file H:/zos24/a4prd3: cache hits 0, misses 0, waits 0 11:54:13.297 00003224 HHC00417I 0:0AAF CKD file H:/zos24/a4res1: cache hits 1, misses 1, waits 0 11:54:13.297 00003224 HHC00417I 0:0AB0 CKD file H:/zos24/a4prd4: cache hits 0, misses 0, waits 0 11:54:13.297 00003224 HHC00201I 0:0583 Tape file T:/herculesawstapefiles/000004.aws, type aws: tape closed 11:54:13.357 00003224 HHC01427I Main storage released 11:54:13.357 00003224 HHC01427I Expanded storage released 11:54:13.357 00003224 HHC01422I Configuration released 11:54:13.389 00003224 HHC01542I HDL: dyngui.dll terminated 11:54:15.957 **** Program to be executed = D:/hercules/4.1/Hercules.exe 11:54:15.957 **** Control file to be used = D:/hercules/zos240.txt 11:54:15.962 Hercules started; process-id=00001AE8 11:54:16.014 00001AE8 HHC00100I Thread id 00002860, prio 5, name 'impl_thread' started 11:54:16.014 00001AE8 HHC00100I Thread id 00002cb0, prio 4, name 'logger_thread' started 11:54:16.014 00001AE8 HHC01413I Hercules version 4.1.0.9426-SDL-g42b533fa (4.1.0.9426) 11:54:16.014 00001AE8 HHC01414I (C) Copyright 1999-2018 by Roger Bowler, Jan Jaeger, and others 11:54:16.014 00001AE8 HHC01417I The SoftDevLabs version of Hercules 11:54:16.014 00001AE8 HHC01415I Build date: Nov 10 2018 at 10:39:02 11:54:16.014 00001AE8 HHC01417I Built with: Microsoft Visual Studio 2008 (MSVC 150030729 1) 11:54:16.014 00001AE8 HHC01417I Build type: Windows MSVC AMD64 host architecture build 11:54:16.014 00001AE8 HHC01417I Modes: S/370 ESA/390 z/Arch 11:54:16.014 00001AE8 HHC01417I Max CPU Engines: 64 11:54:16.014 00001AE8 HHC01417I Using shared libraries 11:54:16.014 00001AE8 HHC01417I Using Fish threads Threading Model 11:54:16.014 00001AE8 HHC01417I Using Error-Checking Mutex Locking Model 11:54:16.014 00001AE8 HHC01417I With Shared Devices support 11:54:16.014 00001AE8 HHC01417I With Dynamic loading support 11:54:16.014 00001AE8 HHC01417I With External GUI support 11:54:16.014 00001AE8 HHC01417I With Partial TCP keepalive support 11:54:16.014 00001AE8 HHC01417I With IPV6 support 11:54:16.014 00001AE8 HHC01417I With HTTP Server support 11:54:16.014 00001AE8 HHC01417I With sqrtl support 11:54:16.014 00001AE8 HHC01417I Without SIGABEND handler 11:54:16.014 00001AE8 HHC01417I With CCKD BZIP2 support 11:54:16.014 00001AE8 HHC01417I With HET BZIP2 support 11:54:16.014 00001AE8 HHC01417I With ZLIB support 11:54:16.014 00001AE8 HHC01417I With Regular Expressions support 11:54:16.014 00001AE8 HHC01417I With Object REXX support 11:54:16.014 00001AE8 HHC01417I Without Regina REXX support 11:54:16.014 00001AE8 HHC01417I With Automatic Operator support 11:54:16.014 00001AE8 HHC01417I Without National Language Support 11:54:16.014 00001AE8 HHC01417I Machine dependent assists: cmpxchg1 cmpxchg4 cmpxchg8 hatomics=msvcIntrinsics 11:54:16.014 00001AE8 HHC01417I Running on: RPINION-PC (Windows-6.2.9200 Intel(R) x64) LP=8, Cores=4, CPUs=1 11:54:16.014 00001AE8 HHC01417I Built with decNumber external package version 3.68.0.79-g53f2512 11:54:16.014 00001AE8 HHC01417I Built with SoftFloat external package version 3.5.0.82-g1c66591 11:54:16.014 00001AE8 HHC01417I Built with telnet external package version 1.0.0.41-ged0ddec 11:54:16.014 00001AE8 HHC00018I Hercules is running in elevated mode 11:54:16.015 00001AE8 HHC02323W This build of Hercules has only partial TCP keepalive support 11:54:16.019 00001AE8 HHC00150I Crypto module loaded (C) Copyright 2003-2016 by Bernard van der Helm 11:54:16.019 00001AE8 HHC01417I Built with crypto external package version 1.0.0.26-gefe199e 11:54:16.019 00001AE8 HHC00151I Activated facility: Message Security Assist 11:54:16.019 00001AE8 HHC00151I Activated facility: Message Security Assist Extension 1, 2, 3 and 4 11:54:16.026 00001AE8 HHC17531W REXX(OORexx) dlopen 'rexx.dll' failed: The specified module could not be found. 11:54:16.026 00001AE8 HHC17511E REXX() Could not enable either Rexx package 11:54:16.026 00001AE8 HHC17511E REXX() Could not enable default Rexx package 11:54:16.026 00001AE8 HHC17500I REXX() Mode : Command 11:54:16.026 00001AE8 HHC17500I REXX() MsgLevel : Off 11:54:16.026 00001AE8 HHC17500I REXX() MsgPrefix : Off 11:54:16.026 00001AE8 HHC17500I REXX() ErrPrefix : Off 11:54:16.026 00001AE8 HHC17500I REXX() Resolver : On 11:54:16.026 00001AE8 HHC17500I REXX() SysPath (24) : On 11:54:16.026 00001AE8 HHC17500I REXX() RexxPath ( 0) : 11:54:16.026 00001AE8 HHC17500I REXX() Extensions ( 8) : .REXX;.rexx;.REX;.rex;.CMD;.cmd;.RX;.rx 11:54:16.029 00001AE8 HHC00111I Thread CPU Time IS available (_POSIX_THREAD_CPUTIME=1) 11:54:16.029 00001AE8 HHC00100I Thread id 00000884, prio 2, name 'Processor CP00' started 11:54:16.029 00001AE8 HHC00811I Processor CP00: architecture mode z/Arch 11:54:16.029 00001AE8 HHC00100I Thread id 00000bf4, prio 7, name 'timer_thread' started 11:54:16.029 00001AE8 HHC00898I Facility( 006_ASN_LX_REUSE ) Enabled for z/Arch 11:54:16.029 00001AE8 HHC00898W Facility( 044_PFPO ) *Enabled for z/Arch 11:54:16.029 00001AE8 HHC02204I MAXCPU set to 1 11:54:16.029 00001AE8 HHC00827I Processor CP00: engine 00 type 0 set: CP 11:54:16.029 00001AE8 HHC02204I NUMCPU set to 1 11:54:16.029 00001AE8 HHC02204I NUMVEC set to 1 11:54:16.029 00001AE8 HHC02256W Command 'HERCPRIO' is deprecated and ignored. 11:54:16.029 00001AE8 HHC02256W Command 'TODPRIO' is deprecated and ignored. 11:54:16.029 00001AE8 HHC02256W Command 'DEVPRIO' is deprecated and ignored. 11:54:16.029 00001AE8 HHC02256W Command 'CPUPRIO' is deprecated and ignored. 11:54:16.030 00001AE8 HHC02204I AUTO_SCSI_MOUNT set to NO 11:54:16.030 00001AE8 HHC02323W This build of Hercules has only partial TCP keepalive support 11:54:16.030 00001AE8 HHC02204I conkpalv set to (3,1,10) 11:54:16.030 00001AE8 HHC01474I Using internal codepage conversion table default 11:54:16.030 00001AE8 HHC02204I CPUMODEL set to 2098 11:54:16.030 00001AE8 HHC02204I CPUSERIAL set to 0E45A4 11:54:16.030 00001AE8 HHC02204I CPUVERID set to 00 11:54:16.030 00001AE8 HHC02204I DIAG8CMD set to DISABLE NOECHO 11:54:16.030 00001AE8 HHC02204I ECPSVM set to disabled 11:54:16.030 00001AE8 HHC01508I HDL: loadable module directory is 'D:/hercules/4.1' 11:54:16.030 00001AE8 HHC02204I MODPATH set to D:/hercules/4.1 11:54:16.030 00001AE8 HHC02204I LEGACYSENSEID set to disabled 11:54:16.030 00001AE8 HHC02204I LOADPARM set to 0AAACSM1 11:54:16.030 00001AE8 HHC02204I LPARNUM set to 01 11:54:16.030 00001AE8 HHC02204I LPARNAME set to HERCULES 11:54:16.037 00001AE8 HHC17003I MAIN storage is 6G (mainsize); storage is not locked 11:54:16.037 00001AE8 HHC02204I MANUFACTURER set to HRC 11:54:16.037 00001AE8 HHC02204I MODEL set to hardware(EMULATOR) capacity(EMULATOR) perm() temp() 11:54:16.037 00001AE8 HHC02204I MOUNTED_TAPE_REINIT set to enabled 11:54:16.037 00001AE8 HHC02204I PANRATE set to 50 11:54:16.037 00001AE8 HHC02204I PLANT set to ZZ 11:54:16.037 00001AE8 HHC02204I SHCMDOPT set to ENABLE NODIAG8 11:54:16.037 00001AE8 HHC02204I TIMERINT set to 50 11:54:16.037 00001AE8 HHC02204I TRACEOPT set to TRADITIONAL 11:54:16.037 00001AE8 HHC02204I TZOFFSET set to -0000 11:54:16.037 00001AE8 HHC17003I EXPANDED storage is 0 (xpndsize); storage is not locked 11:54:16.037 00001AE8 HHC02204I YROFFSET set to 0 11:54:16.039 00001AE8 HHC00100I Thread id 00002420, prio 4, name 'console_connect' started 11:54:16.039 00001AE8 HHC01024I Waiting for console connections on port 3271 11:54:16.039 00001AE8 HHC00414I 0:0D02 CKD file H:/HerculesDasdFiles/LDAV01: cyls 3339 heads 15 tracks 50085 trklen 56832 11:54:16.039 00001AE8 HHC00414I 0:0D03 CKD file H:/HerculesDasdFiles/CFG001: cyls 20000 heads 15 tracks 300000 trklen 56832 11:54:16.040 00001AE8 HHC00414I 0:0A94 CKD file H:/HerculesDasdFiles/SPL001: cyls 3339 heads 15 tracks 50085 trklen 56832 11:54:16.048 00001AE8 HHC00414I 0:0A95 CKD file H:/HerculesDasdFiles/SPOOL2: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.048 00001AE8 HHC00414I 0:0A96 CKD file H:/HerculesDasdFiles/LDAV04: cyls 3339 heads 15 tracks 50085 trklen 56832 11:54:16.056 00001AE8 HHC00414I 0:0A9A CKD file H:/HerculesDasdFiles/LDAV07: cyls 3339 heads 15 tracks 50085 trklen 56832 11:54:16.063 00001AE8 HHC00414I 0:0A9B CKD file H:/HerculesDasdFiles/LDAV08: cyls 3339 heads 15 tracks 50085 trklen 56832 11:54:16.070 00001AE8 HHC00414I 0:0A9D CKD file H:/HerculesDasdFiles/JAIMS1: cyls 3339 heads 15 tracks 50085 trklen 56832 11:54:16.071 00001AE8 HHC00414I 0:0A9F CKD file H:/HerculesDasdFiles/LDAV05: cyls 3339 heads 15 tracks 50085 trklen 56832 11:54:16.071 00001AE8 HHC00414I 0:0D0A CKD file H:/HerculesDasdFiles/LDA023: cyls 32760 heads 15 tracks 491400 trklen 56832 11:54:16.129 00001AE8 HHC00414I 0:0D0B CKD file H:/HerculesDasdFiles/LDAV03: cyls 3339 heads 15 tracks 50085 trklen 56832 11:54:16.138 00001AE8 HHC00414I 0:0D11 CKD file H:/HerculesDasdFiles/LDA074: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.138 00001AE8 HHC00414I 0:0D12 CKD file T:/HerculesDasdFiles/LDA004: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.139 00001AE8 HHC00414I 0:0D13 CKD file T:/HerculesDasdFiles/LDA007: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.139 00001AE8 HHC00414I 0:0D14 CKD file T:/HerculesDasdFiles/LDA008: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.139 00001AE8 HHC00414I 0:0D15 CKD file T:/HerculesDasdFiles/LDA009: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.140 00001AE8 HHC00414I 0:0D16 CKD file T:/HerculesDasdFiles/LDA00A: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.140 00001AE8 HHC00414I 0:0A8A CKD file H:/HerculesDasdFiles/a3sys1: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.140 00001AE8 HHC00414I 0:0A8B CKD file H:/HerculesDasdFiles/a3cfg1: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.141 00001AE8 HHC00414I 0:0A8C CKD file H:/HerculesDasdFiles/a3dis1: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.141 00001AE8 HHC00414I 0:0A8D CKD file H:/HerculesDasdFiles/a3dis2: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.141 00001AE8 HHC00414I 0:0A8E CKD file H:/HerculesDasdFiles/a3dis3: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.142 00001AE8 HHC00414I 0:0A8F CKD file H:/HerculesDasdFiles/a3res1: cyls 30051 heads 15 tracks 450765 trklen 56832 11:54:16.142 00001AE8 HHC00414I 0:0A90 CKD file H:/HerculesDasdFiles/a3res2: cyls 30051 heads 15 tracks 450765 trklen 56832 11:54:16.142 00001AE8 HHC00414I 0:0AA0 CKD file H:/zos24/a4res2: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.143 00001AE8 HHC00414I 0:0AA1 CKD file H:/zos24/a4usr1: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.143 00001AE8 HHC00414I 0:0AA2 CKD file H:/zos24/a4uss1: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.143 00001AE8 HHC00414I 0:0AA3 CKD file H:/zos24/a4uss2: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.143 00001AE8 HHC00414I 0:0AA4 CKD file H:/zos24/a4cfg1: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.144 00001AE8 HHC00414I 0:0AA5 CKD file H:/zos24/a4dis1: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.144 00001AE8 HHC00414I 0:0AA6 CKD file H:/zos24/a4dis2: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.144 00001AE8 HHC00414I 0:0AA7 CKD file H:/zos24/a4dis3: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.144 00001AE8 HHC00414I 0:0AA8 CKD file H:/zos24/a4paga: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.145 00001AE8 HHC00414I 0:0AA9 CKD file H:/zos24/a4pagb: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.145 00001AE8 HHC00414I 0:0AAA CKD file H:/zos24/a4sys1: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.145 00001AE8 HHC00414I 0:0AAB CKD file H:/zos24/a4pagc: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.145 00001AE8 HHC00414I 0:0AAC CKD file H:/zos24/a4prd1: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.146 00001AE8 HHC00414I 0:0AAD CKD file H:/zos24/a4prd2: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.146 00001AE8 HHC00414I 0:0AAE CKD file H:/zos24/a4prd3: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.146 00001AE8 HHC00414I 0:0AAF CKD file H:/zos24/a4res1: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.146 00001AE8 HHC00414I 0:0AB0 CKD file H:/zos24/a4prd4: cyls 10017 heads 15 tracks 150255 trklen 56832 11:54:16.150 00001AE8 HHC00221I 0:0583 Tape file T:/herculesawstapefiles/000004.aws, type aws: format type AWS Format tape file 11:54:16.150 00001AE8 HHC00222I 0:0583 Tape file T:/herculesawstapefiles/000004.aws, type aws: option awstape accepted 11:54:16.150 00001AE8 HHC00222I 0:0583 Tape file T:/herculesawstapefiles/000004.aws, type aws: option maxsizeM accepted 11:54:16.150 00001AE8 HHC00222I 0:0583 Tape file T:/herculesawstapefiles/000004.aws, type aws: option eotmargin accepted 11:54:16.150 00001AE8 HHC00224I 0:0583 Tape file T:/herculesawstapefiles/000004.aws, type aws: display " NT RDY " 11:54:16.170 00001AE8 HHC04100I TunTap64.dll version 3.6.2.4906 initiated 11:54:16.440 00001AE8 HHC04100I TunTap64.dll version 3.6.2.4906 initiated 11:54:16.442 00001AE8 HHC00901I 0:0E20 LCS: Interface tap0, type TAP opened 11:54:16.442 00001AE8 HHC00921I CTC: lcs device port 00: tuntap Multicast assist enabled 11:54:16.442 00001AE8 HHC00935I CTC: lcs device port 00: manual Checksum Offload enabled 11:54:16.443 00001AE8 HHC01541I HDL: dyngui.dll initiated 11:54:21.973 00001AE8 HHC01603I facility enable 73 11:54:21.973 00001AE8 HHC00898W Facility( 073_TRANSACT_EXEC ) Enabled for z/Arch 11:54:28.592 00001AE8 HHC01603I facility enable 50 11:54:28.592 00001AE8 HHC00898W Facility( 050_CONSTR_TRANSACT ) Enabled for z/Arch 11:54:33.672 00001AE8 HHC01603I loadparm 0AAACSM1 11:54:33.672 00001AE8 HHC02204I LOADPARM set to 0AAACSM1 11:54:33.923 00001AE8 HHC01603I ipl 0AAF 11:54:33.934 00001AE8 HHC00811I Processor CP00: architecture mode ESA/390 11:54:33.944 00001AE8 HHC00814I Processor CP00: SIGP Set architecture mode (12) CP00, PARM 00000001: CC 0 11:54:33.944 00001AE8 HHC00811I Processor CP00: architecture mode z/Arch 11:54:33.949 00001AE8 HHC00801I Processor CP00: Operand exception code 0015 ilc 4 11:54:33.949 00001AE8 HHC02324I PSW=0400200080000000 000000002000017C INST=B2342000 STSCH 0(2) store_subchannel 11:54:33.949 00001AE8 HHC02326I V:0000000020012BD8:K:06=00000000 00000000 00000000 00000000 ................ 11:54:33.949 00001AE8 HHC02269I R0=0000000020012C14 R1=0000000000050000 R2=0000000020012BD8 R3=000000000000002E 11:54:33.949 00001AE8 HHC02269I R4=0000000020012BD8 R5=0000000000000000 R6=000000002000F250 R7=0000000000000003 11:54:33.949 00001AE8 HHC02269I R8=00000000FFFFFFF9 R9=0000000020012000 RA=0000000000000005 RB=00000000200007A4 11:54:33.949 00001AE8 HHC02269I RC=00000000A0000000 RD=00000000200006EC RE=00000000A0000172 RF=00000000FFFFFFF8 11:54:33.949 00001AE8 HHC02271I C0=0000000000000200 C1=0000000000004003 C2=0000000000000000 C3=0000000000000000 11:54:33.949 00001AE8 HHC02271I C4=0000000000000000 C5=0000000000000000 C6=00000000FE000000 C7=0000000000000000 11:54:33.949 00001AE8 HHC02271I C8=0000000000000000 C9=0000000000000000 CA=0000000000000000 CB=0000000000000000 11:54:33.949 00001AE8 HHC02271I CC=0000000000000000 CD=0000000000000000 CE=00000000C2000000 CF=0000000000000000 11:54:33.949 00001AE8 HHC00801I Processor CP00: Operand exception code 0015 ilc 4 11:54:33.949 00001AE8 HHC02324I PSW=0400200080000000 000000002000017C INST=B2342000 STSCH 0(2) store_subchannel 11:54:33.949 00001AE8 HHC02326I V:0000000020012BD8:K:06=00000000 00000000 00000000 00000000 ................ 11:54:33.949 00001AE8 HHC02269I R0=0000000020012C14 R1=0000000000070000 R2=0000000020012BD8 R3=000000000000002E 11:54:33.949 00001AE8 HHC02269I R4=0000000020012BD8 R5=0000000000000000 R6=000000002000F250 R7=0000000000000003 11:54:33.949 00001AE8 HHC02269I R8=00000000FFFFFFF9 R9=0000000020012000 RA=0000000000000007 RB=00000000200007A4 11:54:33.949 00001AE8 HHC02269I RC=00000000A0000000 RD=00000000200006EC RE=00000000A0000172 RF=00000000FFFFFFF8 11:54:33.949 00001AE8 HHC02271I C0=0000000000000200 C1=0000000000004003 C2=0000000000000000 C3=0000000000000000 11:54:33.949 00001AE8 HHC02271I C4=0000000000000000 C5=0000000000000000 C6=00000000FE000000 C7=0000000000000000 11:54:33.949 00001AE8 HHC02271I C8=0000000000000000 C9=0000000000000000 CA=0000000000000000 CB=0000000000000000 11:54:33.949 00001AE8 HHC02271I CC=0000000000000000 CD=0000000000000000 CE=00000000C2000000 CF=0000000000000000 11:54:33.961 00001AE8 HHC00814I Processor CP00: SIGP Unassigned (14) CP00, PARM 0000000064000000: CC 1 status 00000002 11:54:35.654 00001AE8 HHC00801I Processor CP00: Operation exception code 0001 ilc 4 11:54:35.654 00001AE8 HHC02324I PSW=0404000080000000 0000000000005B0C INST=B2AF0000 ????? , ? 11:54:35.654 00001AE8 HHC02326I V:0000000000000000:K:0E=000A0000 000130E1 00000000 00000000 ................ 11:54:35.654 00001AE8 HHC02326I V:0000000000000000:K:0E=000A0000 000130E1 00000000 00000000 ................ 11:54:35.654 00001AE8 HHC02269I R0=FFFFFFFF00000000 R1=000000007FFFF000 R2=0000000000FD4A18 R3=D730D95601229780 11:54:35.654 00001AE8 HHC02269I R4=0000000000000000 R5=0000000001D91318 R6=0000000000000000 R7=0000000000FD4A18 11:54:35.654 00001AE8 HHC02269I R8=0000000001D91318 R9=0000000000FD4A18 RA=0000000000005B0C RB=FFFFFFFF00000100 11:54:35.654 00001AE8 HHC02269I RC=0000000000005960 RD=0000000000005F28 RE=0000000001D91318 RF=0000000000000011 11:54:35.654 00001AE8 HHC02271I C0=00800002CE98EE20 C1=000000007C4F8007 C2=000000007FE94D00 C3=0000000180000001 11:54:35.654 00001AE8 HHC02271I C4=0000000100000001 C5=000000007FE94E00 C6=00000000FE000000 C7=000000007C4F8007 11:54:35.654 00001AE8 HHC02271I C8=0000000000000000 C9=0000000000000000 CA=0000000000000000 CB=0000000000000000 11:54:35.654 00001AE8 HHC02271I CC=0000000000000000 CD=000000007C4F8007 CE=00000000C00FF040 CF=0000000000000000 11:54:35.654 00001AE8 HHC00801I Processor CP00: Specification exception code 0006 ilc 4 11:54:35.654 00001AE8 HHC02324I PSW=0404000080000000 0000000000005E36 INST=B2650000 SVS 0,0 set_vector_summary 11:54:35.654 00001AE8 HHC02326I V:0000000000000000:K:0E=000A0000 000130E1 00000000 00000000 ................ 11:54:35.654 00001AE8 HHC02326I V:0000000000000000:K:0E=000A0000 000130E1 00000000 00000000 ................ 11:54:35.654 00001AE8 HHC02269I R0=FFFFFFFF00000000 R1=0000000000000001 R2=0000000000FD4F78 R3=D730D95601229780 11:54:35.654 00001AE8 HHC02269I R4=0000000000FD4A18 R5=0000000000FD4A18 R6=000000000264CDF0 R7=000000000264CDF0 11:54:35.654 00001AE8 HHC02269I R8=0000000001D91318 R9=0000000000FD4A18 RA=0000000000005E3A RB=FFFFFFFF00000100 11:54:35.654 00001AE8 HHC02269I RC=0000000000005960 RD=0000000000005F28 RE=0000000080005BFE RF=0000000000FD4A18 11:54:35.654 00001AE8 HHC02271I C0=00800002CF98EE20 C1=000000007C4F8007 C2=000000007FE94D00 C3=0000000180000001 11:54:35.654 00001AE8 HHC02271I C4=0000000100000001 C5=000000007FE94E00 C6=00000000FE000000 C7=000000007C4F8007 11:54:35.654 00001AE8 HHC02271I C8=0000000000000000 C9=0000000000000000 CA=0000000000000000 CB=0000000000000000 11:54:35.654 00001AE8 HHC02271I CC=0000000000000000 CD=000000007C4F8007 CE=00000000C00FF040 CF=0000000000000000 11:54:35.702 00001AE8 HHC00006I SCLP console interface active 11:54:35.727 00001AE8 HHC00801I Processor CP00: Operation exception code 0001 ilc 6 11:54:35.728 00001AE8 HHC02324I PSW=0404000180000000 0000000001AF3B2A INST=E56100000000 ????? , ? 11:54:35.728 00001AE8 HHC02326I V:0000000000000000:K:0E=000A0000 000130E1 00000000 00000000 ................ 11:54:35.728 00001AE8 HHC02326I V:0000000000000000:K:0E=000A0000 000130E1 00000000 00000000 ................ 11:54:35.728 00001AE8 HHC02269I R0=0000000000000000 R1=0000000001DBAE00 R2=0000000000000000 R3=0000000001DED690 11:54:35.728 00001AE8 HHC02269I R4=0000000000000000 R5=0000000001DB9E00 R6=0000000002B69FA4 R7=0000000002B69800 11:54:35.728 00001AE8 HHC02269I R8=0000000001DB9E00 R9=0000000002B69800 RA=0000000001F07FC0 RB=0000000001FAA6C0 11:54:35.728 00001AE8 HHC02269I RC=0000000001AF4238 RD=0000000002B69978 RE=0000000001AEF660 RF=0000000002B6B610 11:54:35.728 00001AE8 HHC00809I Processor CP00: disabled wait state 0002000080000000 0000000000009064 16:24:33.014 00001AE8 HHC01603I exit 16:24:33.066 00001AE8 HHC01423I Calling termination routines 16:24:33.066 00001AE8 HHC00101I Thread id 00000884, prio 2, name 'Processor CP00' ended 16:24:33.066 00001AE8 HHC00101I Thread id 00002420, prio 4, name 'console_connect' ended 16:24:33.066 00001AE8 HHC00417I 0:0D02 CKD file H:/HerculesDasdFiles/LDAV01: cache hits 0, misses 0, waits 0 16:24:33.066 00001AE8 HHC00417I 0:0D03 CKD file H:/HerculesDasdFiles/CFG001: cache hits 0, misses 0, waits 0 16:24:33.066 00001AE8 HHC00333I 0:0A94 size free nbr st reads writes l2reads hits switches 16:24:33.066 00001AE8 HHC00335I 0:0A94 -------------------------------------------------------------------- 16:24:33.066 00001AE8 HHC00336I 0:0A94 [] 0024308761 004 % 0028 0000000 0000000 0000000 0000000 0000000 16:24:33.066 00001AE8 HHC00338I 0:0A94 H:/HerculesDasdFiles/SPL001 16:24:33.066 00001AE8 HHC00339I 0:0A94 [0] 0024308761 004 % 0028 rw 0000000 0000000 0000000 16:24:33.069 00001AE8 HHC00417I 0:0A95 CKD file H:/HerculesDasdFiles/SPOOL2: cache hits 0, misses 0, waits 0 16:24:33.069 00001AE8 HHC00333I 0:0A96 size free nbr st reads writes l2reads hits switches 16:24:33.069 00001AE8 HHC00335I 0:0A96 -------------------------------------------------------------------- 16:24:33.069 00001AE8 HHC00336I 0:0A96 [] 0553946411 000 % 0825 0000000 0000000 0000000 0000000 0000000 16:24:33.069 00001AE8 HHC00338I 0:0A96 H:/HerculesDasdFiles/LDAV04 16:24:33.069 00001AE8 HHC00339I 0:0A96 [0] 0553946411 000 % 0825 rw 0000000 0000000 0000000 16:24:33.072 00001AE8 HHC00333I 0:0A9A size free nbr st reads writes l2reads hits switches 16:24:33.072 00001AE8 HHC00335I 0:0A9A -------------------------------------------------------------------- 16:24:33.072 00001AE8 HHC00336I 0:0A9A [] 0679942946 000 % 0005 0000000 0000000 0000000 0000000 0000000 16:24:33.072 00001AE8 HHC00338I 0:0A9A H:/HerculesDasdFiles/LDAV07 16:24:33.072 00001AE8 HHC00339I 0:0A9A [0] 0679942946 000 % 0005 rw 0000000 0000000 0000000 16:24:33.075 00001AE8 HHC00333I 0:0A9B size free nbr st reads writes l2reads hits switches 16:24:33.075 00001AE8 HHC00335I 0:0A9B -------------------------------------------------------------------- 16:24:33.075 00001AE8 HHC00336I 0:0A9B [] 0223323353 000 % 0000 0000000 0000000 0000000 0000000 0000000 16:24:33.075 00001AE8 HHC00338I 0:0A9B H:/HerculesDasdFiles/LDAV08 16:24:33.075 00001AE8 HHC00339I 0:0A9B [0] 0223323353 000 % 0000 rw 0000000 0000000 0000000 16:24:33.077 00001AE8 HHC00417I 0:0A9D CKD file H:/HerculesDasdFiles/JAIMS1: cache hits 0, misses 0, waits 0 16:24:33.077 00001AE8 HHC00417I 0:0A9F CKD file H:/HerculesDasdFiles/LDAV05: cache hits 0, misses 0, waits 0 16:24:33.078 00001AE8 HHC00333I 0:0D0A size free nbr st reads writes l2reads hits switches 16:24:33.078 00001AE8 HHC00335I 0:0D0A -------------------------------------------------------------------- 16:24:33.078 00001AE8 HHC00336I 0:0D0A [] 1922033303 000 % 0072 0000000 0000000 0000000 0000000 0000000 16:24:33.078 00001AE8 HHC00338I 0:0D0A H:/HerculesDasdFiles/LDA023 16:24:33.078 00001AE8 HHC00339I 0:0D0A [0] 1922033303 000 % 0072 rw 0000000 0000000 0000000 16:24:33.080 00001AE8 HHC00333I 0:0D0B size free nbr st reads writes l2reads hits switches 16:24:33.080 00001AE8 HHC00335I 0:0D0B -------------------------------------------------------------------- 16:24:33.080 00001AE8 HHC00336I 0:0D0B [] 0208740369 000 % 0020 0000000 0000000 0000000 0000000 0000000 16:24:33.080 00001AE8 HHC00338I 0:0D0B H:/HerculesDasdFiles/LDAV03 16:24:33.080 00001AE8 HHC00339I 0:0D0B [0] 0208740369 000 % 0020 rw 0000000 0000000 0000000 16:24:33.083 00001AE8 HHC00333I 0:0D11 size free nbr st reads writes l2reads hits switches 16:24:33.083 00001AE8 HHC00335I 0:0D11 -------------------------------------------------------------------- 16:24:33.083 00001AE8 HHC00336I 0:0D11 [*] 0006682032 000 % 0000 0000000 0000000 0000000 0000000 0000000 16:24:33.083 00001AE8 HHC00338I 0:0D11 H:/HerculesDasdFiles/LDA074 16:24:33.083 00001AE8 HHC00339I 0:0D11 [0] 0006682032 000 % 0000 rw 0000000 0000000 0000000 16:24:33.085 00001AE8 HHC00417I 0:0D12 CKD file T:/HerculesDasdFiles/LDA004: cache hits 0, misses 0, waits 0 16:24:33.085 00001AE8 HHC00417I 0:0D13 CKD file T:/HerculesDasdFiles/LDA007: cache hits 0, misses 0, waits 0 16:24:33.085 00001AE8 HHC00417I 0:0D14 CKD file T:/HerculesDasdFiles/LDA008: cache hits 0, misses 0, waits 0 16:24:33.085 00001AE8 HHC00417I 0:0D15 CKD file T:/HerculesDasdFiles/LDA009: cache hits 0, misses 0, waits 0 16:24:33.085 00001AE8 HHC00417I 0:0D16 CKD file T:/HerculesDasdFiles/LDA00A: cache hits 0, misses 0, waits 0 16:24:33.086 00001AE8 HHC00417I 0:0A8A CKD file H:/HerculesDasdFiles/a3sys1: cache hits 0, misses 0, waits 0 16:24:33.086 00001AE8 HHC00417I 0:0A8B CKD file H:/HerculesDasdFiles/a3cfg1: cache hits 0, misses 0, waits 0 16:24:33.086 00001AE8 HHC00417I 0:0A8C CKD file H:/HerculesDasdFiles/a3dis1: cache hits 0, misses 0, waits 0 16:24:33.086 00001AE8 HHC00417I 0:0A8D CKD file H:/HerculesDasdFiles/a3dis2: cache hits 0, misses 0, waits 0 16:24:33.086 00001AE8 HHC00417I 0:0A8E CKD file H:/HerculesDasdFiles/a3dis3: cache hits 0, misses 0, waits 0 16:24:33.086 00001AE8 HHC00417I 0:0A8F CKD file H:/HerculesDasdFiles/a3res1: cache hits 0, misses 0, waits 0 16:24:33.086 00001AE8 HHC00417I 0:0A90 CKD file H:/HerculesDasdFiles/a3res2: cache hits 0, misses 0, waits 0 16:24:33.086 00001AE8 HHC00417I 0:0AA0 CKD file H:/zos24/a4res2: cache hits 0, misses 0, waits 0 16:24:33.086 00001AE8 HHC00417I 0:0AA1 CKD file H:/zos24/a4usr1: cache hits 0, misses 0, waits 0 16:24:33.086 00001AE8 HHC00417I 0:0AA2 CKD file H:/zos24/a4uss1: cache hits 0, misses 0, waits 0 16:24:33.086 00001AE8 HHC00417I 0:0AA3 CKD file H:/zos24/a4uss2: cache hits 0, misses 0, waits 0 16:24:33.086 00001AE8 HHC00417I 0:0AA4 CKD file H:/zos24/a4cfg1: cache hits 0, misses 0, waits 0 16:24:33.086 00001AE8 HHC00417I 0:0AA5 CKD file H:/zos24/a4dis1: cache hits 0, misses 0, waits 0 16:24:33.086 00001AE8 HHC00417I 0:0AA6 CKD file H:/zos24/a4dis2: cache hits 0, misses 0, waits 0 16:24:33.086 00001AE8 HHC00417I 0:0AA7 CKD file H:/zos24/a4dis3: cache hits 0, misses 0, waits 0 16:24:33.086 00001AE8 HHC00417I 0:0AA8 CKD file H:/zos24/a4paga: cache hits 0, misses 0, waits 0 16:24:33.086 00001AE8 HHC00417I 0:0AA9 CKD file H:/zos24/a4pagb: cache hits 0, misses 0, waits 0 16:24:33.086 00001AE8 HHC00417I 0:0AAA CKD file H:/zos24/a4sys1: cache hits 11, misses 34, waits 0 16:24:33.087 00001AE8 HHC00417I 0:0AAB CKD file H:/zos24/a4pagc: cache hits 0, misses 0, waits 0 16:24:33.087 00001AE8 HHC00417I 0:0AAC CKD file H:/zos24/a4prd1: cache hits 0, misses 0, waits 0 16:24:33.087 00001AE8 HHC00417I 0:0AAD CKD file H:/zos24/a4prd2: cache hits 0, misses 0, waits 0 16:24:33.087 00001AE8 HHC00417I 0:0AAE CKD file H:/zos24/a4prd3: cache hits 0, misses 0, waits 0 16:24:33.088 00001AE8 HHC00417I 0:0AAF CKD file H:/zos24/a4res1: cache hits 3908, misses 441, waits 0 16:24:33.088 00001AE8 HHC00417I 0:0AB0 CKD file H:/zos24/a4prd4: cache hits 0, misses 0, waits 0 16:24:33.088 00001AE8 HHC00201I 0:0583 Tape file T:/herculesawstapefiles/000004.aws, type aws: tape closed 16:24:33.144 00001AE8 HHC01427I Main storage released 16:24:33.144 00001AE8 HHC01427I Expanded storage released 16:24:33.144 00001AE8 HHC01422I Configuration released 16:24:33.165 00001AE8 HHC01542I HDL: dyngui.dll terminated

**** (last line of logfile above) ****

HercGUI URL: http://www.softdevlabs.com/HercGUI HercGUI support: support@softdevlabs.com

Hercules URL: https://fish-git.github.io/html Hercules support: support@softdevlabs.com

Hercules Emulator Control file...

#

Description:

MaxShutdownSecs: 15

LoadUnit:

RCFile:

LogoFile:

IgnoreParseErrors: 0

HercGUI Version: 1.12.9.3467

#

System parameters

ARCHLVL ENABLE z/Arch

FACILITY ENABLE 006_ASN_LX_REUSE FACILITY ENABLE 044_PFPO

ARCHLVL ENABLE ASN_LX_REUSE

ARCHLVL ENABLE BIT44

ARCHLVL ENABLE BIT48

ARCHLVL ENABLE BIT49

MAXCPU 2

MAXCPU 1

ENGINES CP,CP

ENGINES CP

NUMCPU 2

NUMCPU 1 NUMVEC 1

HERCPRIO 0 TODPRIO -20 DEVPRIO 8 CPUPRIO 15

AUTO_SCSI_MOUNT NO CNSLPORT 3271 CONKPALV (3,1,10) CODEPAGE default CPUMODEL 2098 CPUSERIAL 0E45A4 CPUVERID 00 DEVTMAX 8 DIAG8CMD DISABLE NOECHO ECPSVM NO MODPATH D:/hercules/4.1 LEGACYSENSEID DISABLE LOADPARM 0AAACSM1 LPARNUM 01 LPARNAME HERCULES MAINSIZE 6G MANUFACTURER HRC MODEL EMULATOR "" "" "" MOUNTED_TAPE_REINIT ALLOW OSTAILOR Z/OS PANRATE 50 PGMPRDOS LICENSED PLANT ZZ SHCMDOPT ENABLE NODIAG8 SYSEPOCH 1900 TIMERINT 50 TRACEOPT TRADITIONAL TZOFFSET -0000 XPNDSIZE 0 YROFFSET 0

Display Terminals

0700-0701 3270 0702 3270 * 127.0.0.1

DASD Devices

0D02 3390 H:/HerculesDasdFiles/LDAV01 cu=3990-6 0D03 3390 H:/HerculesDasdFiles/CFG001 cu=3990-6

0A8D 3390 H:/HerculesDasdFiles/SARES1 cu=3990-6

0A94 3390 H:/HerculesDasdFiles/SPL001 cu=3990-6 0A95 3390 H:/HerculesDasdFiles/SPOOL2 cu=3990-6 0A96 3390 H:/HerculesDasdFiles/LDAV04 cu=3990-6 0A9A 3390 H:/HerculesDasdFiles/LDAV07 cu=3990-6 0A9B 3390 H:/HerculesDasdFiles/LDAV08 cu=3990-6 0A9D 3390 H:/HerculesDasdFiles/JAIMS1 cu=3990-6 0A9F 3390 H:/HerculesDasdFiles/LDAV05 cu=3990-6 0D0A 3390 H:/HerculesDasdFiles/LDA023 cu=3990-6 0D0B 3390 H:/HerculesDasdFiles/LDAV03 cu=3990-6 0D11 3390 H:/HerculesDasdFiles/LDA074 cu=3990-6 0D12 3390 T:/HerculesDasdFiles/LDA004 cu=3990-6 0D13 3390 T:/HerculesDasdFiles/LDA007 cu=3990-6 0D14 3390 T:/HerculesDasdFiles/LDA008 cu=3990-6 0D15 3390 T:/HerculesDasdFiles/LDA009 cu=3990-6 0D16 3390 T:/HerculesDasdFiles/LDA00A cu=3990-6

0A8A 3390 H:/HerculesDasdFiles/a3sys1 cu=3990-6 0A8B 3390 H:/HerculesDasdFiles/a3cfg1 cu=3990-6 0A8C 3390 H:/HerculesDasdFiles/a3dis1 cu=3990-6 0A8D 3390 H:/HerculesDasdFiles/a3dis2 cu=3990-6 0A8E 3390 H:/HerculesDasdFiles/a3dis3 cu=3990-6 0A8F 3390 H:/HerculesDasdFiles/a3res1 cu=3990-6 0A90 3390 H:/HerculesDasdFiles/a3res2 cu=3990-6

0AA0 3390 H:/zos24/a4res2 cu=3990-6 0AA1 3390 H:/zos24/a4usr1 cu=3990-6 0AA2 3390 H:/zos24/a4uss1 cu=3990-6 0AA3 3390 H:/zos24/a4uss2 cu=3990-6 0AA4 3390 H:/zos24/a4cfg1 cu=3990-6 0AA5 3390 H:/zos24/a4dis1 cu=3990-6 0AA6 3390 H:/zos24/a4dis2 cu=3990-6 0AA7 3390 H:/zos24/a4dis3 cu=3990-6 0AA8 3390 H:/zos24/a4paga cu=3990-6 0AA9 3390 H:/zos24/a4pagb cu=3990-6 0AAA 3390 H:/zos24/a4sys1 cu=3990-6 0AAB 3390 H:/zos24/a4pagc cu=3990-6 0AAC 3390 H:/zos24/a4prd1 cu=3990-6 0AAD 3390 H:/zos24/a4prd2 cu=3990-6 0AAE 3390 H:/zos24/a4prd3 cu=3990-6 0AAF 3390 H:/zos24/a4res1 cu=3990-6 0AB0 3390 H:/zos24/a4prd4 cu=3990-6

TAPE Devices

0583 3490 T:/herculesawstapefiles/000004.aws awstape maxsizeM=170 eotmargin=131072

CTC Adapters

0E20-0E21 LCS --dev 192.168.1.81 192.168.1.106

Fish-Git commented 4 years ago

I configured one CPU and enabled bits 50 & 73. However, I got
11:54:35.728 00001AE8 HHC00809I Processor CP00: disabled wait state 0002000080000000 0000000000009064
That's a rather piss poor problem report, Richard.
Config file? Log file? Etc...

I was only stating that I tried the procedure that another person had tried.

My apologies, @rpinion (Richard).

If you applied Bob's files to your copy of Hercules (along with the small fix I documented), then z/OS 2.4 should [appear to] successfully IPL when facilities 73 and 50 are enabled.

Your wait state would seem to indicate a hardware configuration error, which is why I asked to see your configuration and log files.

In any case, as I said, I do apologize for my choice of words. My intent was not to insult you, but rather to make clear to you and others of the importance in providing proper documentation when it comes to problem reporting.

It's difficult to help someone when they fail to provide enough information -- information that should have been provided when the problem was first reported.

Fish-Git commented 4 years ago

Quick question for Bob (@rwoodpd) (as well as to anyone else who might be able to answer):

Why are you using hostregs (i.e. hregs) in your code?

You seem to be using it in most of your code but not in all of it. For example, you're using it in maddr_l (dat.h), transaction_begin, transaction_begin_constrained, process_tbegin, nontransactional_store, transaction_end, transaction_abort, and abort_transaction (inline.h), but you're not using it anywhere else (e.g. extract_transaction_nesting_depth for example, not to mention in all of your instructions where you're checking for e.g. regs->contran and then calling abort_transaction).

This does not seem right to me. Shouldn't we be always using regs period, and not hostregs? Wouldn't your use of hostregs break the ability to use TXF (Transactional-Execution Facility) in SIE mode? (i.e. in z/VM, which I haven't tried yet)

Can you (or someone else) please explain this? It doesn't seem right!

Thanks.

Fish-Git commented 4 years ago

Why are you using hostregs (i.e. hregs) in your code?

You're also using it in your CHECK_TRANCTR macro too, used by the EXECUTE_INSTRUCTION macro as each and every instruction executes.

Again, this does not seem right!

(me: confused) %-(

ivan-w commented 4 years ago

This might be to address:

SA22-7832-11 Page: 5-97 Programing Note 1

Basically, transactions are (may) ALWAYS executed at host level, not at guest level. And If a SIE guest has been intercepted, the transaction should be aborted.

ivan-w commented 4 years ago

On non constrained transaction, CC=2 (restartable)... on constrained Transaction, restart from the start. The reason for this is usually that an interrupt became pending and needed servicing for the CPU. (For e.g. z/VM, the SRM Dispatching Minor Time Slice may have fired (in effect, a Clock comparator interrupt from the SIE host)).

ivan-w commented 4 years ago

A SIE intercept may generate a context switch. You cannot rely on guestregs to contain transaction information. The transaction MUST be aborted should a SIE be intercepted.

Fish-Git commented 4 years ago

Ivan wrote:

Fish wrote:

Quick question for Bob (@rwoodpd) (as well as to anyone else who might be able to answer):

Why are you using hostregs (i.e. hregs) in your code?

Can you (or someone else) please explain this? It doesn't seem right!

This might be to address: SA22-7832-11 Page: 5-97 Programing Note 1

Basically, transaction are (may) ALWAYS executed at host level (not at guest level). And If a SIE guest has been intercepted, the transaction should be aborted.

Programing Note 1 on Page 5-97 of both SA22-7832-11 and SA22-7832-12 (the latest and greatest) both say the same exact thing:

(verbatim):

A transaction may be aborted due to causes that are outside the scope of the immediate configu- ration in which it executes. For example, transient events recognized by a hypervisor (such as LPAR or z/VM) may cause a transaction to be aborted.

That doesn't sound like what you're saying, Ivan. You're saying SIE guests cannot ever be allowed to make use of TXF, which to me doesn't make any sense. If a guest operating in SIE mode can manage to complete a transaction without being interrupted by any "transient event" (which I'm presuming means interrupt; the POPs doesn't define what a "transient event" is), then why shouldn't it be allowed to do so?

Yes, if an interrupt ("transient event"?) occurs (or basically anything that causes an SIE intercept), then yes, I can see aborting the SIE guest's transaction. That makes sense.

But if that never occurs during the guest's transaction, why shouldn't it be allowed to complete successfully? Why abort it? (which is basically what you're saying: "transactions are (may) ALWAYS executed at host level, not at guest level"). That doesn't seem right!

I disagree, Ivan. In my opinion Transactions should be allowed at the SIE guest level, so in my opinion the use of hostregs is wrong. We should just be using regs, not hregs.

Unless I'm missing something.

(p.s. Interestingly(?), the only mention of SIE and z/VM seems to be in that one footnote. I can find nowhere else in the entire manual that mentions anything about SIE and/or z/VM as it relates to the Transactional-Execution Facility.)

ivan-w commented 4 years ago

That's not what I said.. I said TXF under SIE is dependent on underlying host conditions. Of course TXF is and should be available under SIE. But the host may sometimes reach a situation where SIE initiated guest transaction needs to be aborted due to host conditions - hence - why when running a transaction under SIE, some provision has to be made about what is happening on the SIE host, and this explains why the implementation needs to check some regs->hostregs stuff eventually!

Fish-Git commented 4 years ago

That's not what I said..

Well that's what your initial statement "Basically, transactions are ... ALWAYS executed at host level, not at guest level." sure makes it seem like! :)

But... I guess when coupled with your subsequent comments I'm willing to concede that that may indeed not be what you actually meant, so I do apologize for the misunderstanding. I did not mean to put words into your mouth.

NOW... exactly where and how in interrupt (-only?) processing SIE considerations need to be taken I'm not quite sure, but I hope you'll at least agree (and this is where I'm hoping @rwoodpd Bob will jump in to clear things up) that the code for the TXF instructions themselves (TBEGIN, TEND, etc) should not be using hregs (hostregs) like it currently is. I'm hoping you'll at least agree that that appears to be a bug! Yes?

That is to say, the TBEGIN, TEND, etc, instructions should not be using hostregs anymore than any other instruction should be using hostregs (which is basically none of them). If, say, MVC or CLI, etc, are not checking for SIE and using hostregs instead of just regs under certain circumstances (and they're not) then neither should TBEGIN or TEND, etc. The current use of hregs (hostregs) in all of the transact.c code (the Transactional-Execution Facility instructions) is an error (bug) IMO and should be fixed to use just regs like all other instructions do. Yes? Agreed? Can we at least agree on that? (Please say yes!)

Bottom line: I'm simply trying to get a little clarity here regarding when/where it's appropriate to be using hostregs instead of just regs with agreement that in the TXF instructions code is not the right place. In interrupt processing? Absolutely! (more than likely) But in the (TXF) instructions themselves? Definitely not!

Yes? Agreed? Can we at least agree on that? (Please say yes!)

I'm also hoping that Bob will jump in here and admit that doing so was an error on his part, an accidental oversight perhaps that he forgot to fix. OR... if not, I'm hoping he can come up with a good explanation as to why he feels/felt that it is/was the correct/appropriate thing to do. (Bob? Hello? Calling Bob! Come in Bob!) ;-)

rwoodpd commented 4 years ago

The actual handling of the Transactional-Execution Facility is at the hardware level, so I think it should always be kept in hostregs.

The registers saved in TBEGIN should be from regs, not hostregs. This is a bug. The checks for regs->contran should be changed.

The big question is whether TBEGIN and/or TBEGINC cause a SIE exit. I don't think there is a way for z/VM (or any other operating system using SIE) to place a guest in and out of transactional mode without issuing the instructions. So, I think any move in/out of SIE should cause an abort. Some of the abort data that is saved should come from the guestregs. I will fix that.

From what I can see, all instructions that can cause a SIE exit are restricted. Additional code does need to be added in the abort logic. I will work on that also.

Note that z/VM 6.4 is the earliest level that supports z/OS guests that use the Transactional-Execution Facility. I will do some testing running a z/OS 2.4 system under z/VM 6.4 to see what happens. Most likely, code will need to be added in sie.c also.

ivan-w commented 4 years ago

A SIE guest with an intercepted SIE should always raise a transaction abort condition. This should be reflected in the SIEBK so that when the hypervisor re-enters SIE (could be on a different CPU) it can reflect the Transaction Abort situation (and restore any saved registers as specified by the GRSM field in TBEGIN/TBEGINC).

However... virtual storage functions should be the only ones allowed to access "host regs" under SIE.

And those functions should be the ones dealing with storage commit/rollback and storage access limits - for example if we try to enforce a certain number of octoword limit (don't worry if a storage location is not accessible: Transaction Abort, SIE Intercept).

Virtual storage functions eventually need to go all the way up to host regs so the host regs needs to be informed there is a guest regs in a transaction.

So maybe MAYBE there may be a requirement for TXF to inform hostregs about transaction state/status.

If done properly, of course, TXF should work in both SIE mode and non-SIE mode!

Fish-Git commented 4 years ago

Bob said:

The actual handling of the Transactional-Execution Facility is at the hardware level, so I think it should always be kept in hostregs.

But just plain regs is the hardware! That is to say, both hostregs and guestregs is "the hardware". When running under SIE and using guestregs, the registers that are being used are the real "hardware registers". Same with storage accesses too. The storage being accessed (fetched from and stored into) is the real machine's storage (i.e. the "hardware").

The big question is whether TBEGIN and/or TBEGINC cause a SIE exit.

I don't see that as an issue at all, big or otherwise. None of the TXF instructions are privileged, so whenever they're executed -- regardless of whether the CPU is in SIE mode or not -- they should just execute normally. Just like any other non-privileged instruction. No SIE exit whatsoever should occur.

So, I think any move in/out of SIE should cause an abort.

I'm not so sure... But contingent upon information to the contrary I tend to agree with you on this point. (For now.)

Some of the abort data that is saved should come from the guestregs. I will fix that.

ALL of the information regarding the abort should come from regs! Not guestregs or hostregs. Just regs.

Additional code does need to be added in the abort logic. I will work on that also.

What "SIE-specific" code do you intend to add to the abort logic? Because in my mind, none of the TXF code needs to know anything about SIE. Why should it care?

Note that z/VM 6.4 is the earliest level that supports z/OS guests that use the Transactional-Execution Facility. I will do some testing running a z/OS 2.4 system under z/VM 6.4 to see what happens.

Lucky you. I have only a partial (bare minimal and very incomplete) copy of z/OS 2.4 to test with which doesn't seem to run correctly at all, but I can't be sure whether that's because of the partial non-standard bare minimal copy I have or whether it's due to problems with our TXF implementation. What I really need a full standard install (i.e. virgin unmodified ADCD).

And I don't have z/VM 6.4 at all either. Only 6.3 (which does me no good).

BUT... I think I may have come up with a way to test TXF in a stand-alone test program manner, thereby completely eliminating the need for either. I just need to think about it some more.

Most likely, code will need to be added in sie.c also.

What code do you propose to add?!

Fish-Git commented 4 years ago

FYI to everyone: FWIW, I have a cleaned up(*) version of Bob's code with ALL use of hostregs changed to just regs instead which appears(**) to run just fine (i.e. identically to Bob's unmodified original code). I believe this would tend to prove my my claim that using hostregs anywhere in TXF code is a bug.

(*) I'm still working on it but once I'm done (a few more days/weeks?) I'll be posting my full report and analysis for peer review. What I mostly did was change all hard coded constants to use #define constants instead as well as rename some fields (not to mention fix his weird non-standard indentation and insert some blank lines here and there to make things easier to read).

I also did some restructuring too, moving the TXF code in dat.h (maddr_l function) and inline.h (abort transaction function) into transact.c where I feel it properly belongs (all TXF code should, IMO, be in transact.c and only transact.c; doing so makes the code easier to manage). I also created a new transact.h header file where the TXF structs NTRANTBL, TPAGEMAP and TDB now live. The only TXF code in hstructs.h is now just the trans stuff. All the other stuff was moved into transact.h.

I'll be releasing all of it along with my analysis in a few days/weeks. I just need to do a few more things first, not the least of which is addressing the complete oversight of channel.c interaction! (Oops! You forgot all about that, didn't you Bob? ;-)

(**) I of course say "appears" due to my incomplete z/OS 2.4 system that I'm testing with. That and the fact that I of course don't know sh*t about z/OS too! What I can say is it appears to run no worse that Bob's unmodified code does. As I said it still doesn't appear to run correctly (and by "correctly" I mean the same way that other z/OS's appear to run (e.g. 1.10, 2.1, 2.3), but as I also said I can't be sure whether that's due to bugs in our TXF code or due to the partial/incomplete minimal non-standard 2.4 install I have. <shrug>

Fish-Git commented 4 years ago

Ivan wrote:

However... virtual storage functions should be the only ones allowed to access "host regs" under SIE.

Which has absolutely nothing to do with TXF! TXF operates on absolute addresses, not virtual addresses. When one of the virtual storage functions is called (vstore8, vstorec, etc) -- regardless of whether it's called by SIE code or not -- the end result is a real address pointing to mainstor. That mainstor address is what TXF operates with and the only thing it cares about. SIE/hostregs has nothing at all to do with TXF.

And those functions should be the ones dealing with storage commit/rollback ...

The commit is done by the TEND instruction if no conflicts are detected and no "rollback" is needed should a transaction fail/abort either, due to the way Bob designed his code (TPAGEMAP shadow page usage). When a transaction is aborted the shadow pages in the pages map are simply discarded. No "rollback" needed.

Virtual storage functions eventually need to go all the way up to host regs so the host regs needs to be informed there is a guest regs in a transaction.

Huh? What are you talking about? Virtual storage functions and hostregs/guestregs? What nonsense is that? The virtual storage functions use regs, not hostregs or guestregs! Wherever regs is pointing -- whether to hostregs or guestregs it matters not -- is what gets used by the virtual storage functions.

And all virtual storage functions all go through the maddr_l address translation function to obtain the real (mainstor) address of the page being accessed, which is the only place where TXF comes into play (and where conflicts are detected and handled).

So maybe MAYBE there may be a requirement for TXF to inform hostregs about transaction state/status.

You're talking gibberish, Ivan. :(

If done properly, of course, TXF should work in both SIE mode and non-SIE mode!

That's the first sensible thing you've said so far! ;-)

rwoodpd commented 4 years ago

Can you be more specific about how your z/OS 2.4 system behaves differently? I have full z/OS 2.4 system that runs the new code with no issues. Can you send me your changes? I will test that on my system. I will also set up a test of running z/OS 2.4 under z/VM 6.4 and let you know the results.

I had not gotten to channel.c yet. As I stated earlier, it is a work in progress.

Also, do you have the coding standards documented? I would be happy to comply with standards.

SDL-Hercules-390 / hyperion

Transactional-Execution Facility design / implementation #263

define PGM_MONITOR_EVENT 0x0040

define PGM_PER_EVENT 0x0080

define PGM_CRYPTO_OPERATION_EXCEPTION 0x0119

if defined( FEATURE_050_CONSTR_TRANSACT_FACILITY )

endif

if defined( FEATURE_051_LOCAL_TLB_CLEARING_FACILITY )

endif

if defined( FEATURE_073_TRANSACT_EXEC_FACILITY )

endif

if defined( FEATURE_074_STORE_HYPER_INFO_FACILITY )

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