FPGA Overlay Build Issues with different Vitis version

[jaeyoun98]

Hi, I'm trying to follow your work, but I've got some issues building the Vitis Database Library GQE Kernels on Alveo U280 card. My current environment settings are:

• OS: Ubuntu 20.04
• FPGA: Alveo U280
• HLS: Vitis 2023.1

[1] I've tried to work with Vitis 2020.1, but there was an issue with accelerator card's platform file. I currently have following platform file: xilinx_u280_gen3x16_xdma_1_202211_1

However, Vitis 2020.1 does not match with the above platform file, and it gives me below compile error. ERROR: [v++ 74-9] Failed to parse /opt/xilinx/platforms/xilinx_u280_gen3x16_xdma_1_202211_1/xilinx_u280_gen3x16_xdma_1_202211_1.xpfmn I think it's because of the version mismatch, but there was no way to get previous version of the platform file. Official Alveo U280 site doesn't support platform files older than 2022.1. Below are the related issues with platform files:

• https://support.xilinx.com/s/question/0D52E000079s1t8SAA/how-to-get-older-versions-of-the-deployment-and-development-target-plaftorm-for-xilinx-avleo-cards?language=en_US
• https://support.xilinx.com/s/question/0D52E00007CfhWaSAJ/vitis-20211-failed-to-parse-the-xpfm-file?language=en_US

[2] Thus I tried to keep up with Vitis 2023.1 and the above platform file, but Vitis 2023.1 had an issue with "dynamic_eval.hpp" source code from 2020.1 Vitis database library. The code basically uses both PIPELINE and INLINE HLS pragmas, but Vitis version after 2020.1 seems to invoke a compile error if INLINE pragma is used with any other pragmas. Below is the error message I got:

ERROR: [v++ 214-272] In function 'void xf::database::details::alu_cell1<ap_uint<32>, ap_uint<32>, ap_uint<32> >(ap_uint<32>, ap_uint<32>, ap_uint<4>, xf::database::details::cell_data<ap_uint<32> >&)', Pragma confli ct happens on 'INLINE' and 'PIPELINE' pragmas: same function (/home/{user}/Vitis_Libraries/database/L1/include/hw/xf_database/dynamic_eval.hpp:216:0)

[3] So I deleted the PIPELINE pragma with all the other settings not changed, but I've got a timing error. WNS was about -0.2ns. When I deleted INLINE pragma instead, I've got a routing verification error. The error message says there are partially confilcted nets.

I wonder how can I deal with these problems. Matching the database library version seems not a good idea, since their kernel designs look quite different from the ones in 2020.1. I'm trying to deal with timing issues (changing kernel frequency, implemenation strategy, or both), but it's not working well.

I deeply appreciate for your great works and hope I can get some helps.

[slacker151]

@jaeyoun98 I have uploaded the U280 platform files for 2021.x, which are no longer available from their official website.

[jaeyoun98]

Thanks, I tried with experiments setup so far and finally nearly made it. Below are two biggest check points during the way here:

• First of all, I think the platform file you've uploaded has some issues, it incurred dpkg error for both commands sudo dpkg -i and sudo apt install. It didn't worked even inside the 18.04 container environment. I've got through this since I found a backup of older platform file too.
• Second, even with all the dependencies are met except the OS version (I'm using Ubuntu 20.04), build process still ended up with negative slacks for my case. However, the value of slack decreased enough to ignore, therefore I built .xclbin manually with appropriate v++ command options given.