Modules accessed through DTM are chip selected based only on DTM address field. In case of Debug RAM, the other control signal is RD (read/not write). RD maps to DTM Read operation, meaning that any other operation (e.g. NOP) will cause a write into DRAM.
Modules accessed through DTM are chip selected based only on DTM address field. In case of Debug RAM, the other control signal is RD (read/not write). RD maps to DTM Read operation, meaning that any other operation (e.g. NOP) will cause a write into DRAM.
https://github.com/SI-RISCV/e200_opensource/blob/2ce55ea9b5b76e47a48865ea47f32e0d17190769/rtl/e203/debug/sirv_debug_module.v#L351
The issue exploits the case for the Debug RAM, but other components may be affected too.
The fix is to condition DTM chip selects by DTM valid read or write operation.