Open JianNingZhang opened 5 years ago
I have the same problem in Ubuntu 18.10.
I have the same problem in Ubuntu 18.10. brabect1's pull request use verilator to simulate testbench and it works well. Hope it helps.
Add SHELL = bash to vsim/bin/run.makefile:
diff --git a/vsim/bin/run.makefile b/vsim/bin/run.makefile index 46a917e..f8fd886 100644 --- a/vsim/bin/run.makefile +++ b/vsim/bin/run.makefile @@ -1,3 +1,4 @@ +SHELL = bash RUN_DIR := ${PWD}
TESTCASE := ${RUN_DIR}/../../riscv-tools/riscv-tests/isa/generated/rv32ui-p-addi
Hello, I am running Verilog simulate testbench according to Chapter 17 of the book, but a fault occurred that
My environment is Ubuntu 16.04 with all essential software installed.