sirv-e-sdk目录下的Makefile脚本如何输出elf和hex文件？

SI-RISCV / e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

https://github.com/riscv-mcu/e203_hbirdv2

Apache License 2.0

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Closed xiaojia102003 closed 4 years ago

xiaojia102003 commented 5 years ago

想跑一下仿真，不想用默认的verilog testcase。但是看了一下Makefile脚本，并没有输出elf和hex的选项。求助大神

xiaojia102003 commented 5 years ago

or when i generate the hex file，how can i transfer the hex file to *.verilog or bin file----> the core can recognize format。。in generate dir？

SophoWang commented 4 years ago

riscv-none-embed-objcopy -O verilog .hex .verilog

riscv-tools/riscv-tests/isa/Makefile

xiaojia102003 commented 4 years ago

riscv-none-embed-objcopy -O verilog .hex .verilog

riscv-tools/riscv-tests/isa/Makefile

Thank you , Got it. :）