Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
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failed in riscv-tools/riscv-tests/isa/generated/rv32ui-p-addi testcase #36
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jackfan00 opened 4 years ago
I simulate riscv-tools/riscv-tests/isa/generated/rv32ui-p-addi testcase, but it failed.
8000019e:
8000019e: 12fd addi t0,t0,-1
800001a0: fe029fe3 bnez t0,8000019e
800001a4: 100083b7 lui t2,0x10008
800001a8: 00838393 addi t2,t2,8 # 10008008 <_start-0x6fff7ff8>
800001ac: 0003a283 lw t0,0(t2)
800001b0: 00040337 lui t1,0x40
800001b4: fff34313 not t1,t1
800001b8: 0062f2b3 and t0,t0,t1 --------stuck here, dont fetch next instruction
800001bc: 0053a023 sw t0,0(t2)
800001c0: 40000293 li t0,1024