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SI-RISCV / e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
https://github.com/riscv-mcu/e203_hbirdv2
Apache License 2.0
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Testbench error #37

Open xiaoliyang1 opened 4 years ago

xiaoliyang1 commented 4 years ago

hello!Because I want to observe the waveform of e203, I use vcs and verdi, but there is no waveform in the output. The problem is as follows:

Fatal: "/home/xly/xly/11.19/e200_opensource/vsim/run/../install/rtl/general/sirv_gnrl_xchecker.v", 41: tb_top.u_e203_soc_top.u_e203_subsys_top.u_e203_subsys_main.u_e203_cpu_top.u_e203_cpu.u_e203_itcm_ctrl.u_sram_icb_ctrl.u_byp_icb_cmd_buf.u_bypbuf_fifo.dp_gt0.wptr_vec_0_dfflrs.sirv_gnrl_xchecker.CHECK_THE_X_VALUE: at time 17594

Error: Oops, detected a X value!!! This should never happen.

$finish called from file "/home/xly/xly/11.19/e200_opensource/vsim/run/../install/rtl/general/sirv_gnrl_xchecker.v", line 41. $finish at simulation time 17594

Toxic-Scofield commented 4 years ago

I have the same problem in modelsim！！！

Toxic-Scofield commented 4 years ago

Hello，have you solved it？