thomascp
commented
4 years ago Hi @jasonlee1001 , After I did this change, something wrong happened during the compile stage.
Changes:
-#SIM_EXEC := vvp ${RUN_DIR}/vvp.exec -none # The free vvp is tooooo slow to run, so just comment it out, and replaced with the fake way below
-SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
+SIM_EXEC := vvp ${RUN_DIR}/vvp.exec -none # The free vvp is tooooo slow to run, so just comment it out, and replaced with the fake way below
+#SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
Compile Error:
../install/tb/tb_top.v:245: Error: $value$plusargs() is a system function, it cannot be called as a task.Did you meet this error? But after I commented out that '$value$plusargs()', I got everything run correctly.
BR, Peng
yaozhaosh
jasonlee1001
sazczmh
請教為何使用 iverilog 仿真會停住 ? 我 make compile 之後在 /vsim/run 得到 vvp.exec 執行後，印完 ITCM 的值就停住了！請問這源碼有用 iverilog 執行過沒問題嗎? Makefile 裡面寫說用 iverilog 會 tooooo slow, 但這看來不是慢，而是沒有辦法仿真，仿真時間無法往前走。 我把所有的 .v 寫到 e200.f , 直接使用 iverilog 去compile *.v , compile 結果看來也是成功的。但執行就是無法讓時間往前走。
有人有遇到同樣的狀況嗎? adminuser@jasonlee:~/work/e200_opensource/vsim$ iverilog -v -s tb_top -f e200.f -D DISABLE_SV_ASSERTION=1 Icarus Verilog version 10.2 (stable) (v10_2)
Copyright 1998-2015 Stephen Williams
This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
translate: /usr/local/lib/ivl/ivlpp -v -L -F"/tmp/ivrlg210b4390c" -f"/tmp/ivrlg10b4390c" -p"/tmp/ivrli10b4390c" | /usr/local/lib/ivl/ivl -v -C"/tmp/ivrlh10b4390c" -C"/usr/local/lib/ivl/vvp.conf" -- - Icarus Verilog Preprocessor version 10.2 (stable) (v10_2)
Copyright (c) 1999-2011,2015 Stephen Williams (steve@icarus.com)
This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. /usr/local/lib/ivl/system.sft: Processing System Function Table file. /usr/local/lib/ivl/vhdl_sys.sft: Processing System Function Table file. /usr/local/lib/ivl/v2005_math.sft: Processing System Function Table file. /usr/local/lib/ivl/va_math.sft: Processing System Function Table file. Using language generation: IEEE1364-2005,no-specify,xtypes,icarus-misc PARSING INPUT ... done, 0.16 seconds. ELABORATING DESIGN ... done, 0.43 seconds. RUNNING FUNCTORS -F cprop ... ... Iteration detected 257 optimizations. ... Iteration detected 0 optimizations. ... Look for dangling constants ... done -F nodangle ... ... scan for dangling signal and event nodes. (scomplete=F, ecomplete=F) ... 1 iterations deleted 46228 dangling signals and 0 events. ... scan for dangling signal and event nodes. (scomplete=T, ecomplete=F) ... 2 iterations deleted 46228 dangling signals and 796 events. ... done CALCULATING ISLANDS ... done, 0.11 seconds. CODE GENERATION ... invoking target_design ... done, 0.25 seconds. STATISTICS lex_string: add_count=102970 hit_count=146754
(編譯完之後 執行 ./a.out) 看起來就是只有執行 time=0 時候的 task, 然後就無法往下了。哪位牛人可以幫忙解一下 ?
adminuser@jasonlee:~/work/e200_opensource/vsim$ ./a.out Compiling VVP ... ... VVP file version 10.2 (stable) (v10_2) Compile cleanup... ... Linking ... Removing symbol tables ... Compiletf functions ... 53662 functors (net_fun pool=2883584 bytes) 36107 logic 0 bufif 0 resolv 1390 signals ... 49554 filters (net_fil pool=6029312 bytes) ... 24661 opcodes (614400 bytes) ... 46609 nets ... 53662 vvp_nets (3145632 bytes) ... 178 arrays (8981 words) ... 18 memories 18 logic (90197 words) 0 real (0 words) ... 6550 scopes ... 0.552 seconds, 77376.0/47872.0/4304.0 KBytes size/rss/shared Running ... ...execute EndOfCompile callbacks ...propagate initialization events ...execute StartOfSim callbacks ...run scheduler !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! ITCM 0x00: 340510730001aa0d ITCM 0x01: ff85051300002517 ITCM 0x02: 01f5222301e52023 ITCM 0x03: 040f416334202f73 ITCM 0x04: 4fa507ff02634fa1 ITCM 0x05: 0c634fad05ff0f63 ITCM 0x06: 0bff05634f8505ff ITCM 0x07: 4f9d0dff00634f95 ITCM 0x16: 2f03f52505130000 ITCM 0x20: 2f8300052f03f065