In testing the model validator for the upcoming SMT-COMP (which we are going to use experimentally for the linear arithmetic logics QF_IDL, QF_RDL, QF_LIA, QF_LRA, QF_LIRA) I did a test run on StarExec with a few solvers, including the version of Yices submitted to the Model Validation track . There was a single case in which a wrong model was reported by the validator, for the problem QF_RDL/.../tms-2-3-light-60.smt2. The offending model is attached. I thought it might interest you. CVC4 produces a model that is accepted by the validator, also attached. I also checked the models with both CVC4 and Yices and the CVC4 models lead to both saying SAT and the Yices model to both saying UNSAT.
In testing the model validator for the upcoming SMT-COMP (which we are going to use experimentally for the linear arithmetic logics QF_IDL, QF_RDL, QF_LIA, QF_LRA, QF_LIRA) I did a test run on StarExec with a few solvers, including the version of Yices submitted to the Model Validation track . There was a single case in which a wrong model was reported by the validator, for the problem QF_RDL/.../tms-2-3-light-60.smt2. The offending model is attached. I thought it might interest you. CVC4 produces a model that is accepted by the validator, also attached. I also checked the models with both CVC4 and Yices and the CVC4 models lead to both saying SAT and the Yices model to both saying UNSAT.
models.tar.gz