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STMicroelectronics / OpenOCD

STMicroelectronics customized version of OpenOCD supporting STM32 MCUs and MPUs
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Segfault when trying to connect to target stm32wlx #6

Closed demute closed 2 years ago

demute commented 3 years ago

I have an stlink-v2 hooked up to a newly designed PCB with an stm32wl55ccu7 but can't seem get OpenOCD working. It connects to the target but as soon as I try to connect with gdb, it segfaults due to a null pointer.

EDIT: I have also tried it out with a nucleo wl55jc1 with an stlink-v3 adapter, same error.

Any ideas?

~$ uname -a Linux 32k 4.15.0-51-generic #55-Ubuntu SMP Wed May 15 14:27:21 UTC 2019 x86_64 x86_64 x86_64 GNU/Linux

~/OpenOCD $ > git rev-parse --short HEAD ff701ce82

Reading symbols from openocd...done. (gdb) run Starting program: /usr/local/bin/openocd -d3 -f interface/stlink.cfg -f target/stm32wlx.cfg [Thread debugging using libthread_db enabled] Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1". Open On-Chip Debugger 0.11.0-rc2+dev-00039-gff701ce82-dirty (2021-08-25-16:35) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html User : 13 1 options.c:63 configuration_output_handler(): debug_level: 3 User : 14 1 options.c:63 configuration_output_handler(): Debug: 15 1 options.c:244 add_default_dirs(): bindir=/usr/local/bin Debug: 16 1 options.c:245 add_default_dirs(): pkgdatadir=/usr/local/share/openocd Debug: 17 1 options.c:246 add_default_dirs(): exepath=/usr/local/bin Debug: 18 1 options.c:247 add_default_dirs(): bin2data=../share/openocd Debug: 19 1 configuration.c:42 add_script_search_dir(): adding /home/manne/.config/openocd Debug: 20 1 configuration.c:42 add_script_search_dir(): adding /home/manne/.openocd Debug: 21 1 configuration.c:42 add_script_search_dir(): adding /usr/local/bin/../share/openocd/site Debug: 22 1 configuration.c:42 add_script_search_dir(): adding /usr/local/bin/../share/openocd/scripts Debug: 23 1 configuration.c:97 find_file(): found /usr/local/bin/../share/openocd/scripts/interface/stlink.cfg Debug: 24 1 command.c:146 script_debug(): command - adapter driver hla Debug: 26 1 command.c:146 script_debug(): command - hla_layout stlink Debug: 28 1 hla_interface.c:242 hl_interface_handle_layout_command(): hl_interface_handle_layout_command Debug: 29 1 command.c:146 script_debug(): command - hla_device_desc ST-LINK Debug: 31 1 hla_interface.c:216 hl_interface_handle_device_desc_command(): hl_interface_handle_device_desc_command Debug: 32 1 command.c:146 script_debug(): command - hla_vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 Debug: 34 1 configuration.c:97 find_file(): found /usr/local/bin/../share/openocd/scripts/target/stm32wlx.cfg Debug: 35 1 configuration.c:97 find_file(): found /usr/local/bin/../share/openocd/scripts/target/swj-dp.tcl Debug: 36 1 command.c:146 script_debug(): command - transport select Info : 37 1 transport.c:276 jim_transport_select(): auto-selecting first available session transport "hla_swd". To override use 'transport select '. Debug: 38 1 hla_transport.c:205 hl_swd_transport_select(): hl_swd_transport_select Debug: 39 1 configuration.c:97 find_file(): found /usr/local/bin/../share/openocd/scripts/mem_helper.tcl Debug: 40 1 command.c:146 script_debug(): command - add_usage_text mrw address Debug: 42 1 command.c:1115 help_add_command(): added 'mrw' help text Debug: 43 1 command.c:146 script_debug(): command - add_help_text mrw Returns value of word in memory. Debug: 45 1 command.c:1128 help_add_command(): added 'mrw' help text Debug: 46 1 command.c:146 script_debug(): command - add_usage_text mrh address Debug: 48 1 command.c:1115 help_add_command(): added 'mrh' help text Debug: 49 1 command.c:146 script_debug(): command - add_help_text mrh Returns value of halfword in memory. Debug: 51 1 command.c:1128 help_add_command(): added 'mrh' help text Debug: 52 1 command.c:146 script_debug(): command - add_usage_text mrb address Debug: 54 1 command.c:1115 help_add_command(): added 'mrb' help text Debug: 55 1 command.c:146 script_debug(): command - add_help_text mrb Returns value of byte in memory. Debug: 57 1 command.c:1128 help_add_command(): added 'mrb' help text Debug: 58 1 command.c:146 script_debug(): command - add_usage_text mmw address setbits clearbits Debug: 60 1 command.c:1115 help_add_command(): added 'mmw' help text Debug: 61 1 command.c:146 script_debug(): command - add_help_text mmw Modify word in memory. new_val = (old_val & ~clearbits) | setbits; Debug: 63 1 command.c:1128 help_add_command(): added 'mmw' help text Debug: 64 1 command.c:146 script_debug(): command - transport select Debug: 65 1 command.c:146 script_debug(): command - transport select Debug: 66 1 command.c:146 script_debug(): command - transport select Debug: 67 1 command.c:146 script_debug(): command - swd newdap stm32wlx cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x6ba02477 Debug: 68 1 hla_tcl.c:111 jim_hl_newtap_cmd(): Creating New Tap, Chip: stm32wlx, Tap: cpu, Dotted: stm32wlx.cpu, 8 params Debug: 69 1 hla_tcl.c:121 jim_hl_newtap_cmd(): Processing option: -irlen Debug: 70 1 hla_tcl.c:121 jim_hl_newtap_cmd(): Processing option: -ircapture Debug: 71 1 hla_tcl.c:121 jim_hl_newtap_cmd(): Processing option: -irmask Debug: 72 1 hla_tcl.c:121 jim_hl_newtap_cmd(): Processing option: -expected-id Debug: 73 1 core.c:1488 jtag_tap_init(): Created Tap: stm32wlx.cpu @ abs position 0, irlen 0, capture: 0x0 mask: 0x0 Debug: 74 1 command.c:146 script_debug(): command - dap create stm32wlx.dap -chain-position stm32wlx.cpu Debug: 75 1 command.c:146 script_debug(): command - transport select Debug: 76 1 command.c:146 script_debug(): command - target create stm32wlx.m4 cortex_m -endian little -dap stm32wlx.dap Info : 77 1 target.c:5657 target_create(): The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD Debug: 78 1 hla_target.c:203 adapter_target_create(): adapter_target_create Debug: 79 1 hla_target.c:173 adapter_init_arch_info(): adapter_init_arch_info Debug: 80 1 command.c:376 register_command(): command 'tpiu' is already registered in '' context Debug: 81 1 command.c:376 register_command(): command 'rtt' is already registered in '' context Debug: 82 1 command.c:146 script_debug(): command - stm32wlx.m4 configure -work-area-phys 0x20008000 -work-area-size 0x2000 -work-area-backup 0 Debug: 83 1 target.c:2161 target_free_all_working_areas_restore(): freeing all working areas Debug: 84 1 target.c:2161 target_free_all_working_areas_restore(): freeing all working areas Debug: 85 1 target.c:2161 target_free_all_working_areas_restore(): freeing all working areas Debug: 86 1 command.c:146 script_debug(): command - flash bank stm32wlx.flash.m4 stm32l4x 0x08000000 0 0 0 stm32wlx.m4 Debug: 88 1 tcl.c:1319 handle_flash_bank_command(): 'stm32l4x' driver usage field missing Debug: 89 1 command.c:146 script_debug(): command - flash bank stm32wlx.otp.m4 stm32l4x 0x1fff7000 0 0 0 stm32wlx.m4 Debug: 91 1 command.c:376 register_command(): command 'stm32l4x' is already registered in '' context Debug: 92 1 command.c:376 register_command(): command 'lock' is already registered in 'stm32l4x' context Debug: 93 1 command.c:376 register_command(): command 'unlock' is already registered in 'stm32l4x' context Debug: 94 1 command.c:376 register_command(): command 'mass_erase' is already registered in 'stm32l4x' context Debug: 95 1 command.c:376 register_command(): command 'option_read' is already registered in 'stm32l4x' context Debug: 96 1 command.c:376 register_command(): command 'option_write' is already registered in 'stm32l4x' context Debug: 97 1 command.c:376 register_command(): command 'trustzone' is already registered in 'stm32l4x' context Debug: 98 1 command.c:376 register_command(): command 'wrp_desc' is already registered in 'stm32l4x' context Debug: 99 1 command.c:376 register_command(): command 'option_load' is already registered in 'stm32l4x' context Debug: 100 1 command.c:376 register_command(): command 'otp' is already registered in 'stm32l4x' context Debug: 101 1 tcl.c:1319 handle_flash_bank_command(): 'stm32l4x' driver usage field missing Debug: 102 1 command.c:146 script_debug(): command - targets stm32wlx.m4 Debug: 104 1 command.c:146 script_debug(): command - adapter speed 500 Debug: 106 1 core.c:1822 jtag_config_khz(): handle jtag khz Debug: 107 1 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value Debug: 108 1 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value Debug: 109 1 command.c:146 script_debug(): command - adapter srst delay 100 Debug: 111 1 command.c:146 script_debug(): command - transport select Debug: 112 1 command.c:146 script_debug(): command - reset_config srst_nogate Debug: 114 1 command.c:146 script_debug(): command - transport select Debug: 115 1 command.c:146 script_debug(): command - stm32wlx.m4 configure -event reset-init

CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.

# Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
# 2 WS compliant with VOS=Range1 and 24 MHz.
mmw 0x58004000 0x00000102 0  ;# FLASH_ACR |= PRFTEN | 2(Latency)
mmw 0x58000000 0x00000091 0  ;# RCC_CR = MSI_ON | MSI Range 24 MHz
# Boost JTAG frequency
adapter speed 4000

Debug: 116 1 command.c:146 script_debug(): command - stm32wlx.m4 configure -event reset-start

Reset clock is MSI (4 MHz)

adapter speed 500

Debug: 117 1 command.c:146 script_debug(): command - stm32wlx.m4 configure -event examine-end global _DUALCORE global _CHIPNAME

# Enable debug during low power modes (uses more power)
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0

# Stop watchdog counters during halt
# DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE004203C 0x00001800 0

if { [set _DUALCORE] } {
    targets $_CHIPNAME.m4

    # enable CPU2 boot after reset and after wakeup from Stop or Standby mode
    # PWR_CR4 |= C2BOOT
    mmw 0x5800040C 0x00008000 0
}

Debug: 118 1 command.c:146 script_debug(): command - stm32wlx.m4 configure -event trace-config

nothing to do

Info : 119 1 server.c:312 add_service(): Listening on port 6666 for tcl connections Info : 120 1 server.c:312 add_service(): Listening on port 4444 for telnet connections Debug: 121 1 command.c:146 script_debug(): command - init Debug: 123 1 command.c:146 script_debug(): command - target init Debug: 125 1 command.c:146 script_debug(): command - target names Debug: 126 1 command.c:146 script_debug(): command - stm32wlx.m4 cget -event gdb-flash-erase-start Debug: 127 1 command.c:146 script_debug(): command - stm32wlx.m4 configure -event gdb-flash-erase-start reset init Debug: 128 1 command.c:146 script_debug(): command - stm32wlx.m4 cget -event gdb-flash-write-end Debug: 129 1 command.c:146 script_debug(): command - stm32wlx.m4 configure -event gdb-flash-write-end reset halt Debug: 130 1 command.c:146 script_debug(): command - stm32wlx.m4 cget -event gdb-attach Debug: 131 1 command.c:146 script_debug(): command - stm32wlx.m4 configure -event gdb-attach halt 1000 Debug: 132 1 target.c:1628 handle_target_init_command(): Initializing targets... Debug: 133 1 hla_target.c:193 adapter_init_target(): adapter_init_target Debug: 134 1 semihosting_common.c:99 semihosting_common_init():
Debug: 135 2 hla_interface.c:109 hl_interface_init(): hl_interface_init Debug: 136 2 hla_layout.c:95 hl_layout_init(): hl_layout_init Debug: 137 2 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value Debug: 138 2 core.c:1789 adapter_khz_to_speed(): have interface set up Debug: 139 2 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value Debug: 140 2 core.c:1789 adapter_khz_to_speed(): have interface set up Info : 141 2 core.c:1565 adapter_init(): clock speed 500 kHz Debug: 142 2 openocd.c:144 handle_init_command(): Debug Adapter init complete Debug: 143 2 command.c:146 script_debug(): command - transport init Debug: 145 2 transport.c:229 handle_transport_init(): handle_transport_init Debug: 146 2 hla_transport.c:156 hl_transport_init(): hl_transport_init Debug: 147 2 hla_transport.c:173 hl_transport_init(): current transport hla_swd Debug: 148 2 hla_interface.c:42 hl_interface_open(): hl_interface_open Debug: 149 2 hla_layout.c:40 hl_layout_open(): hl_layout_open Debug: 150 2 stlink_usb.c:3542 stlink_open(): stlink_open Debug: 151 2 stlink_usb.c:3556 stlink_open(): transport: 4 vid: 0x0483 pid: 0x3744 serial: Debug: 152 2 stlink_usb.c:3556 stlink_open(): transport: 4 vid: 0x0483 pid: 0x3748 serial: Debug: 153 2 stlink_usb.c:3556 stlink_open(): transport: 4 vid: 0x0483 pid: 0x374b serial: Debug: 154 2 stlink_usb.c:3556 stlink_open(): transport: 4 vid: 0x0483 pid: 0x374d serial: Debug: 155 2 stlink_usb.c:3556 stlink_open(): transport: 4 vid: 0x0483 pid: 0x374e serial: Debug: 156 2 stlink_usb.c:3556 stlink_open(): transport: 4 vid: 0x0483 pid: 0x374f serial: Debug: 157 2 stlink_usb.c:3556 stlink_open(): transport: 4 vid: 0x0483 pid: 0x3752 serial: Debug: 158 2 stlink_usb.c:3556 stlink_open(): transport: 4 vid: 0x0483 pid: 0x3753 serial: [New Thread 0x7ffff6743700 (LWP 20785)] Info : 159 4 stlink_usb.c:1346 stlink_usb_version(): STLINK V2J29S7 (API v2) VID:PID 0483:3748 Debug: 160 4 stlink_usb.c:1567 stlink_usb_exit_mode(): MODE: 0x02 Info : 161 5 stlink_usb.c:1378 stlink_usb_check_voltage(): Target voltage: 3.151562 Debug: 162 5 stlink_usb.c:1635 stlink_usb_init_mode(): MODE: 0x01 Debug: 163 5 stlink_usb.c:2956 stlink_dump_speed_map(): Supported clock speeds are: Debug: 164 5 stlink_usb.c:2959 stlink_dump_speed_map(): 4000 kHz Debug: 165 5 stlink_usb.c:2959 stlink_dump_speed_map(): 1800 kHz Debug: 166 5 stlink_usb.c:2959 stlink_dump_speed_map(): 1200 kHz Debug: 167 5 stlink_usb.c:2959 stlink_dump_speed_map(): 950 kHz Debug: 168 5 stlink_usb.c:2959 stlink_dump_speed_map(): 480 kHz Debug: 169 5 stlink_usb.c:2959 stlink_dump_speed_map(): 240 kHz Debug: 170 5 stlink_usb.c:2959 stlink_dump_speed_map(): 125 kHz Debug: 171 5 stlink_usb.c:2959 stlink_dump_speed_map(): 100 kHz Debug: 172 5 stlink_usb.c:2959 stlink_dump_speed_map(): 50 kHz Debug: 173 5 stlink_usb.c:2959 stlink_dump_speed_map(): 25 kHz Debug: 174 5 stlink_usb.c:2959 stlink_dump_speed_map(): 15 kHz Debug: 175 5 stlink_usb.c:2959 stlink_dump_speed_map(): 5 kHz Debug: 176 8 stlink_usb.c:1694 stlink_usb_init_mode(): MODE: 0x02 Debug: 177 8 stlink_usb.c:3886 stlink_usb_open_ap(): AP 0 enabled Debug: 178 9 stlink_usb.c:3629 stlink_open(): Using TAR autoincrement: 4096 Debug: 179 9 core.c:640 adapter_system_reset(): SRST line released Debug: 180 111 hla_interface.c:67 hl_interface_init_target(): hl_interface_init_target Debug: 181 111 stlink_usb.c:1927 stlink_usb_idcode(): IDCODE: 0x6BA02477 Debug: 182 111 command.c:146 script_debug(): command - dap init Debug: 184 111 arm_dap.c:106 dap_init_all(): Initializing all DAPs ... Debug: 185 111 openocd.c:161 handle_init_command(): Examining targets... Debug: 186 111 target.c:1816 target_call_event_callbacks(): target event 19 (examine-start) for core stm32wlx.m4 Debug: 187 111 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0xe000ed00 4 1 Debug: 188 112 target.c:2578 target_read_u32(): address: 0xe000ed00, value: 0x410fc241 Debug: 189 112 cortex_m.c:2039 cortex_m_examine(): Cortex-M4 r0p1 processor detected Debug: 190 112 cortex_m.c:2050 cortex_m_examine(): cpuid: 0x410fc241 Debug: 191 112 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0xe000ef40 4 1 Debug: 192 113 target.c:2578 target_read_u32(): address: 0xe000ef40, value: 0x00000000 Debug: 193 113 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0xe000ef44 4 1 Debug: 194 113 target.c:2578 target_read_u32(): address: 0xe000ef44, value: 0x00000000 Debug: 195 113 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0xe000edf0 4 1 Debug: 196 114 target.c:2578 target_read_u32(): address: 0xe000edf0, value: 0x00030003 Debug: 197 114 target.c:2666 target_write_u32(): address: 0xe000edfc, value: 0x01000000 Debug: 198 114 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe000edfc 4 1 Debug: 199 115 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0xe0002000 4 1 Debug: 200 116 target.c:2578 target_read_u32(): address: 0xe0002000, value: 0x00000260 Debug: 201 116 target.c:2666 target_write_u32(): address: 0xe0002008, value: 0x00000000 Debug: 202 116 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe0002008 4 1 Debug: 203 117 target.c:2666 target_write_u32(): address: 0xe000200c, value: 0x00000000 Debug: 204 117 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe000200c 4 1 Debug: 205 117 target.c:2666 target_write_u32(): address: 0xe0002010, value: 0x00000000 Debug: 206 117 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe0002010 4 1 Debug: 207 118 target.c:2666 target_write_u32(): address: 0xe0002014, value: 0x00000000 Debug: 208 118 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe0002014 4 1 Debug: 209 119 target.c:2666 target_write_u32(): address: 0xe0002018, value: 0x00000000 Debug: 210 119 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe0002018 4 1 Debug: 211 120 target.c:2666 target_write_u32(): address: 0xe000201c, value: 0x00000000 Debug: 212 120 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe000201c 4 1 Debug: 213 120 target.c:2666 target_write_u32(): address: 0xe0002020, value: 0x00000000 Debug: 214 120 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe0002020 4 1 Debug: 215 121 target.c:2666 target_write_u32(): address: 0xe0002024, value: 0x00000000 Debug: 216 121 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe0002024 4 1 Debug: 217 122 cortex_m.c:2150 cortex_m_examine(): FPB fpcr 0x260, numcode 6, numlit 2 Debug: 218 122 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0xe0001000 4 1 Debug: 219 123 target.c:2578 target_read_u32(): address: 0xe0001000, value: 0x40000000 Debug: 220 123 cortex_m.c:1868 cortex_m_dwt_setup(): DWT_CTRL: 0x40000000 Debug: 221 123 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0xe0001fbc 4 1 Debug: 222 124 target.c:2578 target_read_u32(): address: 0xe0001fbc, value: 0x00000000 Debug: 223 124 cortex_m.c:1875 cortex_m_dwt_setup(): DWT_DEVARCH: 0x0 Debug: 224 124 target.c:2666 target_write_u32(): address: 0xe0001028, value: 0x00000000 Debug: 225 124 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe0001028 4 1 Debug: 226 124 target.c:2666 target_write_u32(): address: 0xe0001038, value: 0x00000000 Debug: 227 124 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe0001038 4 1 Debug: 228 125 target.c:2666 target_write_u32(): address: 0xe0001048, value: 0x00000000 Debug: 229 125 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe0001048 4 1 Debug: 230 126 target.c:2666 target_write_u32(): address: 0xe0001058, value: 0x00000000 Debug: 231 126 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe0001058 4 1 Debug: 232 127 cortex_m.c:1924 cortex_m_dwt_setup(): DWT dwtcr 0x40000000, comp 4, watch/trigger Info : 233 127 cortex_m.c:2160 cortex_m_examine(): stm32wlx.m4: hardware has 6 breakpoints, 4 watchpoints Debug: 234 127 target.c:1816 target_call_event_callbacks(): target event 21 (examine-end) for core stm32wlx.m4 Debug: 235 127 target.c:4768 target_handle_event(): target(0): stm32wlx.m4 (hla_target) event: 21 (examine-end) action: global _DUALCORE global _CHIPNAME

# Enable debug during low power modes (uses more power)
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0

# Stop watchdog counters during halt
# DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE004203C 0x00001800 0

if { [set _DUALCORE] } {
    targets $_CHIPNAME.m4

    # enable CPU2 boot after reset and after wakeup from Stop or Standby mode
    # PWR_CR4 |= C2BOOT
    mmw 0x5800040C 0x00008000 0
}

Debug: 236 127 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0xe0042004 4 1 Debug: 237 128 command.c:146 script_debug(): command - mww 0xE0042004 7 Debug: 238 128 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1 Debug: 239 129 target.c:2578 target_read_u32(): address: 0xe000edf8, value: 0x00000000 Debug: 240 130 armv7m.c:371 armv7m_read_core_reg(): read r0 value 0x00001800 Debug: 241 131 armv7m.c:371 armv7m_read_core_reg(): read r1 value 0x00000000 Debug: 242 132 armv7m.c:371 armv7m_read_core_reg(): read r2 value 0x006000d0 Debug: 243 133 armv7m.c:371 armv7m_read_core_reg(): read r3 value 0x00d00000 Debug: 244 134 armv7m.c:371 armv7m_read_core_reg(): read r4 value 0x40020000 Debug: 245 134 armv7m.c:371 armv7m_read_core_reg(): read r5 value 0x58000038 Debug: 246 135 armv7m.c:371 armv7m_read_core_reg(): read r6 value 0x40013000 Debug: 247 136 armv7m.c:371 armv7m_read_core_reg(): read r7 value 0x00000000 Debug: 248 137 armv7m.c:371 armv7m_read_core_reg(): read r8 value 0x00000000 Debug: 249 138 armv7m.c:371 armv7m_read_core_reg(): read r9 value 0x00000000 Debug: 250 139 armv7m.c:371 armv7m_read_core_reg(): read r10 value 0x00000000 Debug: 251 140 armv7m.c:371 armv7m_read_core_reg(): read r11 value 0x00000000 Debug: 252 141 armv7m.c:371 armv7m_read_core_reg(): read r12 value 0x80000000 Debug: 253 141 armv7m.c:371 armv7m_read_core_reg(): read sp value 0x200014f0 Debug: 254 142 armv7m.c:371 armv7m_read_core_reg(): read lr value 0x1fff2b45 Debug: 255 143 armv7m.c:371 armv7m_read_core_reg(): read pc value 0x1fff246a Debug: 256 144 armv7m.c:371 armv7m_read_core_reg(): read xPSR value 0x41000000 Debug: 257 145 armv7m.c:371 armv7m_read_core_reg(): read msp value 0x200014f0 Debug: 258 146 armv7m.c:371 armv7m_read_core_reg(): read psp value 0x00000000 Debug: 259 147 armv7m.c:371 armv7m_read_core_reg(): read pmsk_bpri_fltmsk_ctrl value 0x00000000 Debug: 260 148 armv7m.c:371 armv7m_read_core_reg(): read msp_ns value 0x41000000 Debug: 261 148 armv7m.c:371 armv7m_read_core_reg(): read psp_ns value 0x200014f0 Debug: 262 149 armv7m.c:371 armv7m_read_core_reg(): read msp_s value 0x00000000 Debug: 263 150 armv7m.c:371 armv7m_read_core_reg(): read psp_s value 0x00000000 Debug: 264 151 armv7m.c:371 armv7m_read_core_reg(): read msplim_s value 0x00000000 Debug: 265 152 armv7m.c:371 armv7m_read_core_reg(): read psplim_s value 0x200014f0 Debug: 266 153 armv7m.c:371 armv7m_read_core_reg(): read msplim_ns value 0x00000000 Debug: 267 154 armv7m.c:371 armv7m_read_core_reg(): read psplim_ns value 0x00000000 Debug: 268 155 armv7m.c:371 armv7m_read_core_reg(): read pmsk_bpri_fltmsk_ctrl_s value 0x00000000 Debug: 269 155 armv7m.c:371 armv7m_read_core_reg(): read pmsk_bpri_fltmsk_ctrl_ns value 0x00000000 Debug: 270 157 armv7m.c:369 armv7m_read_core_reg(): read d0 value 0x0000000000000000 Debug: 271 159 armv7m.c:369 armv7m_read_core_reg(): read d1 value 0x0000000000000000 Debug: 272 161 armv7m.c:369 armv7m_read_core_reg(): read d2 value 0x0000000000000000 Debug: 273 162 armv7m.c:369 armv7m_read_core_reg(): read d3 value 0x0000000000000000 Debug: 274 164 armv7m.c:369 armv7m_read_core_reg(): read d4 value 0x0000000000000000 Debug: 275 166 armv7m.c:369 armv7m_read_core_reg(): read d5 value 0x0000000000000000 Debug: 276 167 armv7m.c:369 armv7m_read_core_reg(): read d6 value 0x0000000000000000 Debug: 277 169 armv7m.c:369 armv7m_read_core_reg(): read d7 value 0x0000000000000000 Debug: 278 171 armv7m.c:369 armv7m_read_core_reg(): read d8 value 0x0000000000000000 Debug: 279 173 armv7m.c:369 armv7m_read_core_reg(): read d9 value 0x0000000000000000 Debug: 280 174 armv7m.c:369 armv7m_read_core_reg(): read d10 value 0x0000000000000000 Debug: 281 176 armv7m.c:369 armv7m_read_core_reg(): read d11 value 0x0000000000000000 Debug: 282 178 armv7m.c:369 armv7m_read_core_reg(): read d12 value 0x0000000000000000 Debug: 283 180 armv7m.c:369 armv7m_read_core_reg(): read d13 value 0x0000000000000000 Debug: 284 181 armv7m.c:369 armv7m_read_core_reg(): read d14 value 0x0000000000000000 Debug: 285 183 armv7m.c:369 armv7m_read_core_reg(): read d15 value 0x0000000000000000 Debug: 286 184 armv7m.c:371 armv7m_read_core_reg(): read fpscr value 0x00000000 Debug: 287 185 hla_target.c:289 adapter_debug_entry(): entered debug state in core mode: Thread at PC 0x1fff246a, target->state: halted Debug: 288 185 target.c:1816 target_call_event_callbacks(): target event 0 (gdb-halt) for core stm32wlx.m4 Debug: 289 185 target.c:1816 target_call_event_callbacks(): target event 1 (halted) for core stm32wlx.m4 Debug: 290 185 hla_target.c:331 adapter_poll(): halted: PC: 0x1fff246a Debug: 292 185 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe0042004 4 1 Debug: 293 186 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0xe004203c 4 1 Debug: 294 187 command.c:146 script_debug(): command - mww 0xE004203C 6144 Debug: 296 188 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe004203c 4 1 Debug: 297 189 command.c:146 script_debug(): command - flash init Debug: 299 190 tcl.c:1385 handle_flash_init_command(): Initializing flash devices... Debug: 300 190 command.c:146 script_debug(): command - nand init Debug: 302 190 tcl.c:498 handle_nand_init_command(): Initializing NAND devices... Debug: 303 191 command.c:146 script_debug(): command - pld init Debug: 305 191 pld.c:206 handle_pld_init_command(): Initializing PLDs... Debug: 306 191 command.c:146 script_debug(): command - tpiu init Info : 307 191 gdb_server.c:3503 gdb_target_start(): starting gdb server for stm32wlx.m4 on 3333 Info : 308 191 server.c:312 add_service(): Listening on port 3333 for gdb connections Info : 309 6059 server.c:100 add_connection(): accepting 'gdb' connection on tcp/3333 Debug: 310 6059 breakpoints.c:384 breakpoint_clear_target_internal(): Delete all breakpoints for target: stm32wlx.m4 Debug: 311 6059 breakpoints.c:524 watchpoint_clear_target(): Delete all watchpoints for target: stm32wlx.m4 Debug: 312 6059 target.c:1816 target_call_event_callbacks(): target event 22 (gdb-attach) for core stm32wlx.m4 Debug: 313 6059 target.c:4768 target_handle_event(): target(0): stm32wlx.m4 (hla_target) event: 22 (gdb-attach) action: halt 1000 Debug: 314 6059 command.c:146 script_debug(): command - halt 1000 Debug: 316 6060 target.c:3249 handle_halt_command(): - Debug: 317 6060 hla_target.c:418 adapter_halt(): adapter_halt Debug: 318 6060 hla_target.c:421 adapter_halt(): target was already halted Debug: 319 6060 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0xe0042000 4 1 Debug: 320 6061 target.c:2578 target_read_u32(): address: 0xe0042000, value: 0x10016497 Info : 321 6061 stm32l4x.c:1643 stm32l4_probe(): device idcode = 0x10016497 (STM32WLEx/WL5x - Rev 1.1 : 0x1001) Debug: 322 6061 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0x58004020 4 1 Debug: 323 6062 target.c:2578 target_read_u32(): address: 0x58004020, value: 0x3ffff0aa Info : 324 6062 stm32l4x.c:1659 stm32l4_probe(): RDP level 0 (0xAA) Debug: 325 6062 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0x1fff75e0 2 1 Debug: 326 6063 target.c:2602 target_read_u16(): address: 0x1fff75e0, value: 0x0100 Info : 327 6063 stm32l4x.c:1702 stm32l4_probe(): flash size = 256kbytes

Thread 1 "openocd" received signal SIGSEGV, Segmentation fault. 0x00005555556b38e9 in stm32l4_probe (bank=0x555555c59390) at src/flash/nor/stm32l4x.c:1861 1861 if (armv7m->debug_ap->ap_num == 1) (gdb) bt

0 0x00005555556b38e9 in stm32l4_probe (bank=0x555555c59390) at src/flash/nor/stm32l4x.c:1861

1 0x00005555556b3d78 in stm32l4_auto_probe (bank=0x555555c59390) at src/flash/nor/stm32l4x.c:1946

2 0x00005555555f2597 in get_flash_bank_by_num (num=0, bank=0x7fffffffdde0) at src/flash/nor/core.c:299

3 0x0000555555626a27 in gdb_new_connection (connection=0x555555c777e0) at src/server/gdb_server.c:1004

4 0x000055555562e056 in add_connection (service=0x555555c73f80, cmd_ctx=0x555555c07260) at src/server/server.c:101

5 0x000055555562f1ae in server_loop (command_context=0x555555c07260) at src/server/server.c:543

6 0x00005555555ad3fd in openocd_thread (argc=6, argv=0x7fffffffe0e8, cmd_ctx=0x555555c07260) at src/openocd.c:318

7 0x00005555555ad4fa in openocd_main (argc=6, argv=0x7fffffffe0e8) at src/openocd.c:360

8 0x00005555555acda6 in main (argc=6, argv=0x7fffffffe0e8) at src/main.c:39

(gdb) quit

EDIT: debug_ap is null, which ultimately causes the segfault.

tarek-bochkati commented 3 years ago

Hi demute,

Thank you for reporting the issue. This is probably caused by the usage of "interface/stlink.cfg" which do not support STM32WL multicore debugging.

Could you please switch to -f "interface/stlink-dap.cfg" and check if you have still the same issue.

Best Regards, Tarek

demute commented 3 years ago

Hi tarek-bochkati,

Thank you for your reply. Changing the interface to stlink-dap solved the problem right away, thanks! Now I'm able to connect to the target and I get no segfault. However, for some reason I'm not able to flash it, OpenOCD says target needs a reset and then it fails to erase the flash. I haven't had time to trace down the root cause of this problem yet but I guess it's unrelated to the original issue. If you think so as well you are welcome to close this issue, or, if you know the exact reason, you are very welcome to give me a hint.

With kind regards, Manne

Open On-Chip Debugger 0.11.0-rc2+dev-00039-gff701ce82-dirty (2021-08-25-16:35) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html DEPRECATED! use 'adapter speed' not 'adapter_khz' Info : auto-selecting first available session transport "dapdirect_swd". To override use 'transport select '. none separate

Info : Listening on port 6666 for tcl connections Info : Listening on port 4444 for telnet connections Info : STLINK V2J29S7 (API v2) VID:PID 0483:3748 Info : Target voltage: 3.163922 Info : Unable to match requested speed 500 kHz, using 480 kHz Info : Unable to match requested speed 500 kHz, using 480 kHz Info : clock speed 480 kHz Info : stlink_dap_op_connect(connect) Info : SWD DPIDR 0x6ba02477 Info : stm32wlx.m4: hardware has 6 breakpoints, 4 watchpoints Info : starting gdb server for stm32wlx.m4 on 3333 Info : Listening on port 3333 for gdb connections Info : accepting 'gdb' connection on tcp/3333 Info : device idcode = 0x10016497 (STM32WLEx/WL5x - Rev 1.1 : 0x1001) Info : RDP level 0 (0xAA) Info : flash size = 256kbytes Info : flash mode : single-bank Info : device idcode = 0x10016497 (STM32WLEx/WL5x - Rev 1.1 : 0x1001) Info : RDP level 0 (0xAA) Info : OTP size is 1024 bytes, base address is 0x1fff7000 undefined debug reason 8 - target needs reset Info : Unable to match requested speed 500 kHz, using 480 kHz Info : Unable to match requested speed 500 kHz, using 480 kHz target halted due to debug-request, current mode: Thread xPSR: 0x01000000 pc: 0x1fff2b6c msp: 0x20001508 Info : Unable to match requested speed 500 kHz, using 480 kHz Info : Unable to match requested speed 500 kHz, using 480 kHz target halted due to debug-request, current mode: Thread xPSR: 0x01000000 pc: 0x1fff2b6c msp: 0x20001508 Error: failed erasing sectors 0 to 5 Error: flash_erase returned -4 ...