TIM: dirty state SR register after invoke TIM_Base_SetConfig()

STMicroelectronics / STM32CubeF7

STM32Cube MCU Full Package for the STM32F7 series - (HAL + LL Drivers, CMSIS Core, CMSIS Device, MW libraries plus a set of Projects running on all boards provided by ST (Nucleo, Evaluation and Discovery Kits))

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TIM: dirty state SR register after invoke TIM_Base_SetConfig() #110

Closed KamilDuljas closed 5 months ago

KamilDuljas commented 6 months ago

After invoke TIM_Base_SetConfig SR register contains set update event flag. This flag is generate by line:

https://github.com/STMicroelectronics/stm32f7xx_hal_driver/blob/8c7077398fb8c4481f7d843e25b4f1471971b442/Src/stm32f7xx_hal_tim.c#L6967

It should be cleared by HAL before giving up control to main code.

Proposal fix:

 /* Generate an update event to reload the Prescaler
     and the repetition counter (only for advanced timer) value immediately */
  TIMx->EGR = TIM_EGR_UG;
// Clear flag
TIMx->SR = ~(TIM_IT_UPDATE);

ALABSTM commented 6 months ago

Hi @KamilDuljas,

You are right about the fact that the UIF bit in the SR is set upon setting bit UG in the EGR by software. This point will be forwarded to our development teams. They will conclude whether it is a bug that should be fixed or whether this is to serve a certain purpose. I will keep you informed. Thank you for having reported.

With regards,

ALABSTM commented 6 months ago

ST Internal Reference: 169543

RJMSTM commented 5 months ago

Fixed in commit 0495bf0fda6f592b034a4267f8e7c7b816e4196e