Inconsistent information about overrun detection in ADC

[KamilDuljas]

In reference manual for stm32Fx6, chapter 15.8.2 we read:

...When EOCS = 1, overrun detection is automatically enabled. Thus, each time a conversion is complete, EOC is set and the ADC_DR register can be read. The overrun management is the same as when the DMA is used..

But in register map we read:

Bit 10 EOCS: End of conversion selection This bit is set and cleared by software. 0:The EOC bit is set at the end of each sequence of regular conversions. Overrun detection is enabled only if DMA=1. 1: The EOC bit is set at the end of each regular conversion. Overrun detection is enabled.

[RJMSTM]

Hello @KamilDuljas,

Thank you for this report. We will get back to you as soon as we analyze it further. This may take some time. Thank you for your comprehension.

With regards,

[RJMSTM]

Hello @KamilDuljas,

In RM 0.385 section 15.8.2

When EOCS = 1, overrun detection is automatically enabled

it's the same think in register map we read

The Overrun detection is enabled when the EOCS=1

Best regards, Rania

[KamilDuljas]

Hi, this issue is about overrun management.

"The overrun management is the same as when the DMA is used.."

Versus

"Overrun detection is enabled only if DMA=1."

What's true? Overrun management works always or not?

[RJMSTM]

Hello @KamilDuljas

This description states that ADC overrun detection mechanism is the same (data register write while no previous read acknowledge) whatever data fetch by DMA (EOCS = 0 and DMA = 1) or fetch by CPU (EOCS = 1).

[KamilDuljas]

Ok thanks, I understood now.