Closed FRASTM closed 4 years ago
Hi @FRASTM , this PR was already integrated in https://github.com/zephyrproject-rtos/hal_stm32.
Please read this post from me on the ST community page https://community.st.com/s/feed/0D50X0000C5TOy8
Mainly SystemCoreClock
gets divided by 2. I think that's a bug.
should the patch in this post be integrated in this PR?
Hi InterCreate,
Thank you for your involvement. For the moment, we do not process pull-requests. Hopefully, this will change soon enough.
In the meanwhile, I would suggest that you create an issue to report what you pointed out. Mentioning the link to your post on the ST Community would be helpful too.
With regards,
Hi @FRASTM,
Thank you for this report. Pull-requests are not processed for the moment. However, @intercreate created an issue where he mentioned your pull-request.
Please allow me to close this pull-request. Further discussions regarding this aspect will continue in the frame of the issue above mentioned.
With regards,
ST Internal Reference: 79947
When configuring the PLL > 80MHz, an intermediate step is needed with AHB prescaler set to 2 before setting the actual value. Then the AHB prescaler 1 must be set, though
Signed-off-by: Francois Ramu francois.ramu@st.com
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