Eth: Clear Rx and Tx pending bit before processing - Githubissues

STMicroelectronics / STM32CubeH7

STM32Cube MCU Full Package for the STM32H7 series - (HAL + LL Drivers, CMSIS Core, CMSIS Device, MW libraries plus a set of Projects running on all boards provided by ST (Nucleo, Evaluation and Discovery Kits))

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Eth: Clear Rx and Tx pending bit before processing #192

Closed engycz closed 2 years ago

engycz commented 2 years ago

If Rx bit is clear after processing this situation could happen:

Packet 1 received
RI bit 0->1 -> interrupt invoked
Start processing the packet 1
End processing the packet 1
Packet 2 received
Clear RI bit 1->0
End of interrupt routine
No interrupt invoked for packet 2
Packet 3 received
RI bit 0->1 -> interrupt invoked
Start processing the packet 2
End processing the packet 2
Start processing the packet 3
End processing the packet 3

Result:

Packet 2 is not processed upon receive

When the Rx/Tx pending bit is clear before processing this situation could happen:

Packet 1 received
RI bit 0->1 -> interrupt invoked
Clear RI bit 1->0
Packet 2 received
Start processing the packet 1
End processing the packet 1
Start processing the packet 2
End processing the packet 2
End of interrupt routine
RI bit active -> interrupt invoked
No Rx packet in the queue
End of interrupt routine

Result:

Rx interrupt routine invoked - no data in the queue -> OK

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ST-dot-com commented 2 years ago

This pull request has been refused, the Contribution License Agreement must be signed.