Closed jealcuna closed 2 years ago
Hi @jealcuna,
Please allow me to close this thread as it is a duplicate of #216 .
With regards,
Hi @jealcuna,
Please allow me to close this thread as it is a duplicate of #216 .
With regards,
But the issue persist even when mask was fixed. So I am not sure if both issues are related.
Describe the set-up
Describe the bug QUAD SPI has a fifo threshold register that can accept values from 0 to 31. It has 5 bits size. The 5 bit can not be modified making a possible configuration to 16 bytes 0xf.
How To Reproduce
Follow the steps to reproduce the bug here https://github.com/STMicroelectronics/STM32CubeH7/issues/216#issue-1226165798
Modify the mask to 0x1f
Try to set fifo threshold with values greater than 15, and the fifth bit always keep 0.