search

STMicroelectronics / STM32CubeH7

STM32Cube MCU Full Package for the STM32H7 series - (HAL + LL Drivers, CMSIS Core, CMSIS Device, MW libraries plus a set of Projects running on all boards provided by ST (Nucleo, Evaluation and Discovery Kits))
https://www.st.com/en/embedded-software/stm32cubeh7.html
Other
490 stars 302 forks source link

HAL_PWREx_HoldCore(PWR_CORE_CPU1) Does not stop execution in CM7 #227

Closed MuhammadJahanzebTariq closed 1 year ago

MuhammadJahanzebTariq commented 2 years ago

I am using the template with CM7 as gated and CM4 core boot. This behavior works fine. In my application, CM4 runs on bank1 and CM7 runs on Bank 2. One sector on Bank 2 is dedicated to store application data. So CM4 tries to write to that sector, which gives performance issues as CM7 is executing in the same bank. What i tried is: Hold the CM7 core (or if i can stop it somehow), write in the sector 1 of Bank2 , and then resume CM7. I tried to Hold the CM7 via HAL_PWREx_HoldCore(PWR_CORE_CPU1); but it doesnt stop execution. Can you please help

HBOSTM commented 1 year ago

Hello @MuhammadJahanzebTariq ,

The STM32CubeH7 is providing an example of Hold Mechanism that you may refer to it. The example is similar to your use case. It shows how to use the hold mechanism to allow the system to be re-initialized by a master CPU.

Indeed, CPU1 (Cortex-M7) and CPU2 (Cortex-M4) are booting at once. System Init, System clock, voltage scaling and L1-Cache configuration are done by CPU1 (Cortex-M7). In the meantime, Domain D2 is put in STOP mode (CPU2: Cortex-M4 in deep sleep mode) to save power consumption. When system initialization is finished, CPU1 (Cortex-M7) could release CPU2 (Cortex-M4) when needed by means of HSEM notification or by any D2 Domain wakeup source (SEV,EXTI..).

With Regards,

HBOSTM commented 1 year ago

Hello @MuhammadJahanzebTariq ,

First of all, thank you for this contribution. If this problem is solved, please allow me to close it.

Best Regards,