Closed kasjer closed 1 year ago
Hello @kasjer,
Thank you for this contribution, from my side there is no problem in HAL_SPI_Init Configuration, Would you please give us more details about how you got this issue? And share the code you have used to reproduce this issue.
Best Regards,
Problem was visible when nucleo board was communicating with SPI display with SPI touch screen controller. Original project runs on mynewt OS with hal driver from ST. Let me check if I can prepare simple code that can be tested in STM32CubeIDE.
best regards.
Hi, I can not reproduce this behavior any more event with mynewt code. Maybe something else played a role in what I have seen before. Thank you for your attention and I apologize for making a problem.
Describe the set-up nucle- h723zg board + SPI LCD connected to SPI1
Describe the bug SPI is reconfigured between LCD and touch screen usages (16MHz and 1MHz). Both use Mode0 so there should be no changes on clock line during transition since
MasterKeepIOState
is set toSPI_MASTER_KEEP_IO_STATE_ENABLE
all the time. Below lines causes the SCK line to go high https://github.com/STMicroelectronics/stm32h7xx_hal_driver/blob/733af5f9315c077ad1965a5a2743d1aace779818/Src/stm32h7xx_hal_spi.c#L394-L399 Later SCK line is corrected after execution of: https://github.com/STMicroelectronics/stm32h7xx_hal_driver/blob/733af5f9315c077ad1965a5a2743d1aace779818/Src/stm32h7xx_hal_spi.c#L461-L465 ...where CFG register is corrected. But in the meantime extra SCK pulse is generated resulting in invalid transmission.How To Reproduce I suspect that simply calling HAL_SPI_Init() twice can result in this behavior, as it seems that CFG2 register bit that should have AFCNTR bit set whole the time, but is cleared for brief period of time.
Additional context It looks like having SPI_CFG2_AFCNTR set in first write to CFG2 solves the problem.
Screenshots