DMA HAL enables FIFO Error interrupt even if the FIFO is not enabled

[multiplemonomials]

Describe the set-up

• NUCLEO_H743ZI2
• arm-none-eabi-gcc 13.2.1

Describe the bug Working on the mbed-ce/mbed-os DMA SPI code for STM32H7, I observed that my code was going into the DMA error ISR handler during DMA transfers. This happened intermittently and for no apparent reason, and the error bit was the FIFO error flag. Eventually I found this forum thread that described the issue and the fix well. Basically, the FIFO error flag can set under "nominal" conditions just due to the DMA controller having issues acquiring the MCU internal bus.

While this can indicate that perhaps you need to enable the FIFO or reduce bus contention in your project, it is not an error that should fail the DMA transfer, I believe. For my application, I simply turned off the error flag and saw perfect behavior. (it probably helps that the SPI peripheral has its own FIFO so data won't be immediately lost of this happens

How To Reproduce Unfortunately I don't have an easy way to reproduce this one, but me and that person on the forum both had it occur during "normal" application operation. In my case, it was happening when I was doing DMA SPI transfers with a pretty standard configuration (DMA controller in direct mode).

Additional context In my application, I fixed it by changing this line to:

      // Only enable FIFO error if FIFO is enabled (direct mode disabled).
      // In direct mode this flag can set spuriously due to bus contention.
      if(((DMA_Stream_TypeDef *)hdma->Instance)->FCR & DMA_SxFCR_DMDIS)
      {
        ((DMA_Stream_TypeDef *)hdma->Instance)->FCR |= DMA_IT_FE;
      }

This way the FE flag will not generate an error interrupt if the DMA

[ALABSTM]

ST Internal Reference: 192903

[ALABSTM]

Hi @multiplemonomials,

Thank you for your report. The point looks relevant. It has been reported to our development teams. Let's wait for their feedback.

With regards,