bug: clock divider /3 /5 /6 /7 errors

[h00g]

The behaviour of the clock divider deviates from the specification.

The /3 output trigger every third of fifth input over 8 so in average it triggers ever fourth input. The /5 /6 and /7 output all trigger every eigth input but with an offset from /8 by -3, -2 and -1 input respectively.

[JerrySievert]

hm. not only am I not able to replicate this behavior, but there are tests in SynthDevKit (which is where the clock module logic lives) that tests this.

but, that's still not rack, so I went ahead and refactored the whole project (I was planning on doing that anyways, so don't worry), and added tests at the step() level, and I'm still not able to replicate what you're seeing.

can you create a patch that shows the issue and share it? my thought is that you're not triggering with enough "voltage", and are not seeing what you expect. the input triggers occur at 1.5, and drop back out when under 1.5.

if you're curious, here are the test results:

Clock Divider Initial Clock
  ✓ clock divider is instantiated
  ✓ output 1 is not active
  ✓ output 2 is not active
  ✓ output 3 is not active
  ✓ output 4 is not active
  ✓ output 5 is not active
  ✓ output 6 is not active
  ✓ output 7 is not active
  ✓ output 8 is not active

Clock Divider First Clock
  ✓ clock divider is instantiated
  ✓ output 1 is active
  ✓ output 2 is not active
  ✓ output 3 is not active
  ✓ output 4 is not active
  ✓ output 5 is not active
  ✓ output 6 is not active
  ✓ output 7 is not active
  ✓ output 8 is not active

Clock Divider Second Clock
  ✓ clock divider is instantiated
  ✓ output 1 is active
  ✓ output 2 is active
  ✓ output 3 is not active
  ✓ output 4 is not active
  ✓ output 5 is not active
  ✓ output 6 is not active
  ✓ output 7 is not active
  ✓ output 8 is not active

Clock Divider Third Clock
  ✓ clock divider is instantiated
  ✓ output 1 is active
  ✓ output 2 is not active
  ✓ output 3 is active
  ✓ output 4 is not active
  ✓ output 5 is not active
  ✓ output 6 is not active
  ✓ output 7 is not active
  ✓ output 8 is not active

Clock Divider Fourth Clock
  ✓ clock divider is instantiated
  ✓ output 1 is active
  ✓ output 2 is active
  ✓ output 3 is not active
  ✓ output 4 is active
  ✓ output 5 is not active
  ✓ output 6 is not active
  ✓ output 7 is not active
  ✓ output 8 is not active

Clock Divider Fifth Clock
  ✓ clock divider is instantiated
  ✓ output 1 is active
  ✓ output 2 is not active
  ✓ output 3 is not active
  ✓ output 4 is not active
  ✓ output 5 is active
  ✓ output 6 is not active
  ✓ output 7 is not active
  ✓ output 8 is not active

Clock Divider Sixth Clock
  ✓ clock divider is instantiated
  ✓ output 1 is active
  ✓ output 2 is active
  ✓ output 3 is active
  ✓ output 4 is not active
  ✓ output 5 is not active
  ✓ output 6 is active
  ✓ output 7 is not active
  ✓ output 8 is not active

Clock Divider Seventh Clock
  ✓ clock divider is instantiated
  ✓ output 1 is active
  ✓ output 2 is not active
  ✓ output 3 is not active
  ✓ output 4 is not active
  ✓ output 5 is not active
  ✓ output 6 is not active
  ✓ output 7 is active
  ✓ output 8 is not active

Clock Divider Eighth Clock
  ✓ clock divider is instantiated
  ✓ output 1 is active
  ✓ output 2 is active
  ✓ output 3 is not active
  ✓ output 4 is active
  ✓ output 5 is not active
  ✓ output 6 is not active
  ✓ output 7 is not active
  ✓ output 8 is active

Clock Divider Ninth Clock
  ✓ clock divider is instantiated
  ✓ output 1 is active
  ✓ output 2 is not active
  ✓ output 3 is not active
  ✓ output 4 is not active
  ✓ output 5 is not active
  ✓ output 6 is not active
  ✓ output 7 is not active
  ✓ output 8 is not active

PASSED: 90
FAILED: 0

[h00g]

Interesting. I'll definitely present a patch and maybe video, hopefully later today.

As preliminary info I tested with the following as triggers.

• fundamental: LFO-1
• AS: BPM clock, the trigger modules
• bogaudio modules: manual

Links https://github.com/AScustomWorks/AS/blob/master/README.md https://github.com/bogaudio/BogaudioModules/blob/master/README.md

For the LFO-1 I used a square wave as trigger input to the clock divider and tried different pulse widths to see if it has any effect, which it didn't. In both 0-10 V or the balanced -5 to 5 V modes the 1.5 V is reached.

No irregularities were seen in the /1 /2 /4 and /8 output.

I used fundamental scope and AS steps to visually and numerically support the behaviour reported.

[JerrySievert]

ok, let me know what you find.

just curious as to what version of rack and what platform you're running on, though: Mac, linux, or windows.

[h00g]

I'm on Windows and 0.5.1. My wife use Linux and the same version so I may be able to test both.

[h00g]

Here's the fundamental only approach.

/3 shows (second scope) the 3+5 over 8 beats case described above.

/5 generates one beat per 8, not one ever 5.

/6 show the same issue as /5

/7 too

Here's the rack file. SynthKit clock divider problem.zip

[JerrySievert]

I'm going to say that you have something else going on - either you are using enough modules that not every step is sent to all modules, not enough cpu on your machine to run rack itself, or some sort of other error in windows.

I don't say this lightly - I also brought up a windows 10 VM, installed a new copy of Rack 0.5.1, and installed a copy of SynthKit downloaded from the plugins page, and put together a very small patch of just the LFO-1 and ClockDivider:

rack.zip

that's an MPEG of the clock divider, working as expected - the logic is very simple for this clock divider:

    if (states[i] == true) {
      outputs[i].value = in;
      lights[i].value = 1.0f;
    } else {
      outputs[i].value = 0;
      lights[i].value = 0;
    }

if the light is on, it outputs the same value as the input. if the light is off, it's set to 0. so, either signal, or no signal. what determines the light being on is a little more complicated, as it times the length of pulse and divides it in half for the pulse width, but again, if the light is on, so is the signal.

[h00g]

The video you shared shows exactly the same behaviour as I described.

The /3 output lights up in the following pattern (0=off and 1=on) with a space every third 100 100 001 001 000 010 ... Isn't it supposed to be 100 100 100 100 100 ...?

The issue I described for /5 /6 and /7 are also in the video with these lighting up exactly once every 8 pulses, not every 5th, 6th and 7th of them?

The documentation says

/1 11111111 11111111 ok /2 01010101 01010101 ok /3 00100100 10010010 actual 00100001 00100001... /4 00010001 00010001 ok /5 00001000 01000010 actual 00001000 00001000 ... /6 00000100 00010000 actual 00000100 00000100 ... /7 00000010 00000100 actual 00000010 00000010 ... /8 00000001 00000001 ok

---[ more info ]--- Rack v0.5.1 with my attached and screendumped patch use 8 threads and an average CPU usage of 1.2% on my Intel Core i7 2600K 8-core system with 16 GB RAM and a GTX 970 GPU.

The SynthKit plugin was installed on 2018-02-19 but the plugin.dll file contains no version information that I can convey to you but the zip-file it was installed from is called SynthKit-0.5.5-win.zip so I assume it's v0.5.5.

Next I took my ubuntu virtual machine (VirtualBox) and installed Rack 0.5.1 and SynthKit 0.5.5. With that I connected a Fundamental/LFO-1 square wave to the SynthKit/ClockDivider and got the same result as documented above for /3, /5, /6 and /7.

Next I installed Rack 0.5.1 and SynthKit 0.5.5 on a laptop running Ubuntu and got the same results.

[JerrySievert]

even downloading your patch, I'm still seeing every clock fire in order the way it is supposed to: 3, 5, 6, and 7 all fire off for the correct duration, in the correct order:

• 1
• 1 2
• 1 3
• 1 2 4
• 1 5
• 1 2 3 6
• 1 7
• 1 2 4 8

I'm happy to take another video in either macOS or windows - I don't have have X11 running on any of my linux instances currently, or I'd do the same there.

one thing that you can do is install the NYSTHI plugin pack, and run the multi-track recorder, put the input of what's going in to the clock divider into channel 1, the output from 1 on the clock divider into channel 2, and the output from 3 on the clock divider to channel 3. save to a file, let it run for 10 seconds, and send me the resulting wav file - that will let me see exactly what inputs you are seeing, and exactly what outputs you are seeing. I just used the same patch you attached to this issue, if you want to do the same, that works for me.

[JerrySievert]

this is only an 8 step clock divider, it uses base 8, not base 10, and just jumps through the first 8 clock states over and over again.

[JerrySievert]

ah, I see, my documentation is out of date

let me fix that.

[h00g]

So it's not supposed to work like documented but that truncated to 8 steps and then resetting from the beginning?

I was, as you more can imagine, very confused with that you then couldn't figure out what I reported, despite giving a 32 beat example initially.

[JerrySievert]

your example was showing failure on every beat for them.

[h00g]

My report was that "The behaviour of the clock divider deviates from the specification." and I showed the specified (i.e expected) behaviour versus the actual output in the visual.

Is it ok to try to build a clock divider found what I was after based on your source?