Some of the sign extensions weren't working entirely correctly (It only affected one specific operation in a very rare case which is why I didn't catch it before). I also re-did how the FSGNJ operations work, since they were behaving poorly. I also added a simplistic RISC-V assembly file to test them. This is the last functional update I'm making to the RISC-V core, I'm moving on now to fixing up the comments/documentation and maybe creating a larger, more comprehensive FPU test assembly file for the program that moves through every FPU operation.
Some of the sign extensions weren't working entirely correctly (It only affected one specific operation in a very rare case which is why I didn't catch it before). I also re-did how the FSGNJ operations work, since they were behaving poorly. I also added a simplistic RISC-V assembly file to test them. This is the last functional update I'm making to the RISC-V core, I'm moving on now to fixing up the comments/documentation and maybe creating a larger, more comprehensive FPU test assembly file for the program that moves through every FPU operation.