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SebastianBoe / turborav

A self-contained computer stack hobby project
BSD 2-Clause "Simplified" License
15 stars 2 forks source link

APB memory interface #2

Closed SebastianBoe closed 9 years ago

SebastianBoe commented 10 years ago

Create a memory module with an APB interface. The APB infrastructure necessary for connecting multiple APB slaves in a complexity-scalable manner. Create an APB interface for turborav to the APB bus.

SebastianBoe commented 10 years ago

A rom that implements the slave interface is in progress.

SebastianBoe commented 9 years ago

The Ravv core has successfully fetched instructions from the ROM and executed them. With the caveats; Need to resolve RAW hazards with nops. Can't read or write memory.

But still, hooray!

This issue can be closed when we have a read-write memory integrated into Soc and Ravv that the Ravv is able to use.

terjr commented 9 years ago

Can this issue be closed?

SebastianBoe commented 9 years ago

Not until i have a working load/store test that proves it works.

SebastianBoe commented 9 years ago

Not knowing anything about buses I naively believed that AHB must be more complex to implement than APB since it is faster. In fact, the opposite is true. Reading the AHB spec I know see that

SebastianBoe commented 9 years ago

Finished a new version of the memory system that has a single-cycle latency. "Proven" to work with a sanity store & load test. Comprehensive testing will be done by the RISC-V test suite.