Attempt at limiting memory writes by keeping SH4 registers in host registers as long as possible.
The effectiveness of this cache is limited by the percentage of jitted instructions: Each fallback to interpreter forces the JIT to commit all registers to memory.
But still.
I hoped for some performance gain =/
But alas, nothing.
To the point I'm wondering if this is worth the complexity... Although I guess it would be easy to turn on/off later to see if this actually helps or not, when the JIT is more mature.
Attempt at limiting memory writes by keeping SH4 registers in host registers as long as possible. The effectiveness of this cache is limited by the percentage of jitted instructions: Each fallback to interpreter forces the JIT to commit all registers to memory. But still. I hoped for some performance gain =/ But alas, nothing.
To the point I'm wondering if this is worth the complexity... Although I guess it would be easy to turn on/off later to see if this actually helps or not, when the JIT is more mature.