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Senryoku / Deecy

Experimental Dreamcast emulator written in Zig
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Investigate the weird hack needed by Crazy Taxi in the audio branch #31

Closed Senryoku closed 2 months ago

Senryoku commented 2 months ago

Crazy Taxi clears the disable fiq bit before clearing the interrupt in a FIQ, leading to a re-entry. Not sure if this is actually an issue, but it's definitely weird, and causes a very bad crash. During the second entry the Link Register is set to inside the FIQ routine and the program jumps back in it when it's supposed to return to Supervisor mode, leading to a bad reading in the stack and restoring a null CPSR, caushing the crash. I added a workaround for this specific case which let Crazy Taxi run without regressing elsewhere afaik, but I don't think this is an actual solution: https://github.com/Senryoku/arm7/commit/e56729af3c376500be4c6bf4a967bb100b6cd14e#diff-f223cc6d411b9182210dcc2386c5d5663d7d011518b666cd790caec2bf40b912R575

Trace of the crash (with some comments):

Setting CPSR from current mode arm7.RegisterMode.Supervisor to 60000013: arm7.CPSR{ .m = arm7.RegisterMode.Supervisor, .t = false, .f = false, .i = false, ._ = 0, .v = false, .c = true, .z = true, .n = false }
Changing mode from arm7.RegisterMode.Supervisor to arm7.RegisterMode.FastInterrupt
Saved SPSR for arm7.RegisterMode.FastInterrupt: arm7.CPSR{ .m = arm7.RegisterMode.Supervisor, .t = false, .f = false, .i = false, ._ = 0, .v = false, .c = true, .z = true, .n = false }
PC: 00000C34
LR: 000005F0
SP: 0000B200
R0: 00000001   R8: 60000013
R1: 00000040   R9: 00000001
R2: 00000000   R10: 00000040
R3: FFFFFFFF   R11: 00802800
R4: 001D0000   R12: 0000B200
R5: 00000000   R13: 0000B200
R6: 0000D500   R14: 000005F0
R7: 00802800   R15: 00000C3C
audio_callback: frame_count=441, available=6
   [00000BF4] 00001FFF HalfwordDataTransferRegisterOffset
   [00000BF8] 00802800 addeq r2,r0,r0,LSL#16
   [00000BFC] 0000C000 andeq r12,r0,r0
   [00000C00] 00000060 andeq r0,r0,r0,RRX
   [00000C04] 0000B260 andeq r11,r0,r0,ROR#4
   [00000C08] 00000500 andeq r0,r0,r0,LSL#10
   [00000C0C] 0000A20C andeq r10,r0,r12,LSL#4
   [00000C10] E5DC8008 ldrb r8,[r12, #0x8]
   [00000C14] E3580001 cmp r8,#001
   [00000C18] 0A000005 beq 0x1c
   [00000C1C] E59FD4D4 ldr sp,[pc, #0x4D4]
   [00000C20] E59FC4D4 ldr r12,[pc, #0x4D4]
   [00000C24] E59FB4D4 ldr r11,[pc, #0x4D4]
   [00000C28] E59FA4D4 ldr r10,[pc, #0x4D4]
   [00000C2C] E3A00001 mov r0,#001
   [00000C30] E5CC0008 strb r0,[r12, #0x8]
 > [00000C34] E14F8000 mrs r8, SPSR
   [00000C38] E92D41FF stmdb sp!, {r0,r1,r2,r3,r4,r5,r6,r7,r8,lr}
   [00000C3C] E5DB0500 ldrb r0,[r11, #0x500]
info(aica): arm7: (FastInterrupt) [0C38] E92D41FF - stmdb sp!, {r0,r1,r2,r3,r4,r5,r6,r7,r8,lr} - SP:0000B200 - LR:000005F0
info(aica): arm7: (FastInterrupt) [0C3C] E5DB0500 - ldrb r0,[r11, #0x500]  - SP:0000B1D8 - LR:000005F0 <= Check int code
info(aica): arm7: (FastInterrupt) [0C40] E3500002 - cmp r0,#002            - SP:0000B1D8 - LR:000005F0
info(aica): arm7: (FastInterrupt) [0C44] 0A00003A - beq 0xf0               - SP:0000B1D8 - LR:000005F0
info(aica): arm7: (FastInterrupt) [0C48] E3500001 - cmp r0,#001            - SP:0000B1D8 - LR:000005F0
info(aica): arm7: (FastInterrupt) [0C4C] 0A000008 - beq 0x28               - SP:0000B1D8 - LR:000005F0
info(aica): arm7: (FastInterrupt) [0C74] E3A000D4 - mov r0,#0D4            - SP:0000B1D8 - LR:000005F0 |
info(aica): arm7: (FastInterrupt) [0C78] E58B0094 - str r0,[r11, #0x94]    - SP:0000B1D8 - LR:000005F0 \-> TIMER_B = D4
info(aica): arm7: (FastInterrupt) [0C7C] E59C0020 - ldr r0,[r12, #0x20]    - SP:0000B1D8 - LR:000005F0 |
info(aica): arm7: (FastInterrupt) [0C80] E2800001 - add r0,r0,#001         - SP:0000B1D8 - LR:000005F0 |
info(aica): arm7: (FastInterrupt) [0C84] E58C0020 - str r0,[r12, #0x20]    - SP:0000B1D8 - LR:000005F0 \-> (B220)* += 1
info(aica): arm7: (FastInterrupt) [0C88] E59C0038 - ldr r0,[r12, #0x38]    - SP:0000B1D8 - LR:000005F0 |
info(aica): arm7: (FastInterrupt) [0C8C] E2800001 - add r0,r0,#001         - SP:0000B1D8 - LR:000005F0 |
info(aica): arm7: (FastInterrupt) [0C90] E58C0038 - str r0,[r12, #0x38]    - SP:0000B1D8 - LR:000005F0 \-> (B238)* += 1
info(aica): arm7: (FastInterrupt) [0C94] E5DC0003 - ldrb r0,[r12, #0x3]    - SP:0000B1D8 - LR:000005F0
info(aica): arm7: (FastInterrupt) [0C98] E3500001 - cmp r0,#001            - SP:0000B1D8 - LR:000005F0     (B203)* == 1 ?
info(aica): arm7: (FastInterrupt) [0C9C] 0A00000F - beq 0x44               - SP:0000B1D8 - LR:000005F0 ---
info(aica): arm7: (FastInterrupt) [0CA0] E3A00001 - mov r0,#001            - SP:0000B1D8 - LR:000005F0 |
info(aica): arm7: (FastInterrupt) [0CA4] E5CC0003 - strb r0,[r12, #0x3]    - SP:0000B1D8 - LR:000005F0 \-> (B203)* = 1
info(aica): arm7: (FastInterrupt) [0CA8] E10F0000 - mrs r0, CPSR           - SP:0000B1D8 - LR:000005F0 |
info(aica): arm7: (FastInterrupt) [0CAC] E3C000C0 - bic r0,r0,#0C0         - SP:0000B1D8 - LR:000005F0 |
info(aica): arm7: (FastInterrupt) [0CB0] E129F000 - msr CPSR_cf, r0        - SP:0000B1D8 - LR:000005F0 \-> Clear F bit
Setting CPSR from current mode arm7.RegisterMode.FastInterrupt to 80000011: arm7.CPSR{ .m = arm7.RegisterMode.FastInterrupt, .t = false, .f = false, .i = false, ._ = 0, .v = false, .c = false, .z = false, .n = true }
info(aica): arm7: (FastInterrupt) [001C] EA0002FB - b 0xbf4                - SP:0000B1D8 - LR:00000CB8 - Re-entry in FIQ
info(aica): arm7: (FastInterrupt) [0C10] E5DC8008 - ldrb r8,[r12, #0x8]    - SP:0000B1D8 - LR:00000CB8
info(aica): arm7: (FastInterrupt) [0C14] E3580001 - cmp r8,#001            - SP:0000B1D8 - LR:00000CB8
info(aica): arm7: (FastInterrupt) [0C18] 0A000005 - beq 0x1c               - SP:0000B1D8 - LR:00000CB8
info(aica): arm7: (FastInterrupt) [0C34] E14F8000 - mrs r8, SPSR           - SP:0000B1D8 - LR:00000CB8
PC: 00000C34
LR: 00000CB8
SP: 0000B1D8
R0: 80000011   R8: 60000013
R1: 00000040   R9: 00000001
R2: 00000000   R10: 00000040
R3: FFFFFFFF   R11: 00802800
R4: 001D0000   R12: 0000B200
R5: 00000000   R13: 0000B1D8
R6: 0000D500   R14: 00000CB8
R7: 00802800   R15: 00000C3C
   [00000BF4] 00001FFF HalfwordDataTransferRegisterOffset
   [00000BF8] 00802800 addeq r2,r0,r0,LSL#16
   [00000BFC] 0000C000 andeq r12,r0,r0
   [00000C00] 00000060 andeq r0,r0,r0,RRX
   [00000C04] 0000B260 andeq r11,r0,r0,ROR#4
   [00000C08] 00000500 andeq r0,r0,r0,LSL#10
   [00000C0C] 0000A20C andeq r10,r0,r12,LSL#4
   [00000C10] E5DC8008 ldrb r8,[r12, #0x8]
   [00000C14] E3580001 cmp r8,#001
   [00000C18] 0A000005 beq 0x1c
   [00000C1C] E59FD4D4 ldr sp,[pc, #0x4D4]
   [00000C20] E59FC4D4 ldr r12,[pc, #0x4D4]
   [00000C24] E59FB4D4 ldr r11,[pc, #0x4D4]
   [00000C28] E59FA4D4 ldr r10,[pc, #0x4D4]
   [00000C2C] E3A00001 mov r0,#001
   [00000C30] E5CC0008 strb r0,[r12, #0x8]
 > [00000C34] E14F8000 mrs r8, SPSR
   [00000C38] E92D41FF stmdb sp!, {r0,r1,r2,r3,r4,r5,r6,r7,r8,lr}
   [00000C3C] E5DB0500 ldrb r0,[r11, #0x500]
info(aica): arm7: (FastInterrupt) [0C38] E92D41FF - stmdb sp!, {r0,r1,r2,r3,r4,r5,r6,r7,r8,lr} - SP:0000B1D8 - LR:00000CB8
info(aica): arm7: (FastInterrupt) [0C3C] E5DB0500 - ldrb r0,[r11, #0x500]  - SP:0000B1B0 - LR:00000CB8
info(aica): arm7: (FastInterrupt) [0C40] E3500002 - cmp r0,#002            - SP:0000B1B0 - LR:00000CB8
info(aica): arm7: (FastInterrupt) [0C44] 0A00003A - beq 0xf0               - SP:0000B1B0 - LR:00000CB8
info(aica): arm7: (FastInterrupt) [0C48] E3500001 - cmp r0,#001            - SP:0000B1B0 - LR:00000CB8
info(aica): arm7: (FastInterrupt) [0C4C] 0A000008 - beq 0x28               - SP:0000B1B0 - LR:00000CB8
info(aica): arm7: (FastInterrupt) [0C74] E3A000D4 - mov r0,#0D4            - SP:0000B1B0 - LR:00000CB8
info(aica): arm7: (FastInterrupt) [0C78] E58B0094 - str r0,[r11, #0x94]    - SP:0000B1B0 - LR:00000CB8
info(aica): arm7: (FastInterrupt) [0C7C] E59C0020 - ldr r0,[r12, #0x20]    - SP:0000B1B0 - LR:00000CB8
info(aica): arm7: (FastInterrupt) [0C80] E2800001 - add r0,r0,#001         - SP:0000B1B0 - LR:00000CB8
info(aica): arm7: (FastInterrupt) [0C84] E58C0020 - str r0,[r12, #0x20]    - SP:0000B1B0 - LR:00000CB8
info(aica): arm7: (FastInterrupt) [0C88] E59C0038 - ldr r0,[r12, #0x38]    - SP:0000B1B0 - LR:00000CB8
info(aica): arm7: (FastInterrupt) [0C8C] E2800001 - add r0,r0,#001         - SP:0000B1B0 - LR:00000CB8
info(aica): arm7: (FastInterrupt) [0C90] E58C0038 - str r0,[r12, #0x38]    - SP:0000B1B0 - LR:00000CB8
info(aica): arm7: (FastInterrupt) [0C94] E5DC0003 - ldrb r0,[r12, #0x3]    - SP:0000B1B0 - LR:00000CB8
info(aica): arm7: (FastInterrupt) [0C98] E3500001 - cmp r0,#001            - SP:0000B1B0 - LR:00000CB8 (B203)* == 1 ? YES!
info(aica): arm7: (FastInterrupt) [0C9C] 0A00000F - beq 0x44               - SP:0000B1B0 - LR:00000CB8 ---
info(aica): arm7: (FastInterrupt) [0CE0] E3A00080 - mov r0,#080            - SP:0000B1B0 - LR:00000CB8
info(aica): arm7: (FastInterrupt) [0CE4] E58B00A4 - str r0,[r11, #0xA4]    - SP:0000B1B0 - LR:00000CB8 -- Clear interrupt (writes to SCIRE)
info(aica): arm7: (FastInterrupt) [0CE8] EAFFFFD8 - b 0xffffff68           - SP:0000B1B0 - LR:00000CB8
info(aica): arm7: (FastInterrupt) [0C50] E3A00001 - mov r0,#001            - SP:0000B1B0 - LR:00000CB8
info(aica): arm7: (FastInterrupt) [0C54] E5CB0504 - strb r0,[r11, #0x504]  - SP:0000B1B0 - LR:00000CB8 -- INTClear
info(aica): arm7: (FastInterrupt) [0C58] E5CB0504 - strb r0,[r11, #0x504]  - SP:0000B1B0 - LR:00000CB8 -- INTClears
info(aica): arm7: (FastInterrupt) [0C5C] E5CB0504 - strb r0,[r11, #0x504]  - SP:0000B1B0 - LR:00000CB8 -- INTClears
info(aica): arm7: (FastInterrupt) [0C60] E5CB0504 - strb r0,[r11, #0x504]  - SP:0000B1B0 - LR:00000CB8 -- INTClears
info(aica): arm7: (FastInterrupt) [0C64] E8BD41FF - ldmia sp!, {r0,r1,r2,r3,r4,r5,r6,r7,r8,lr} - SP:0000B1B0 - LR:00000CB8
info(aica): arm7: (FastInterrupt) [0C68] E169F008 - msr SPSR_cf, r8        - SP:0000B1D8 - LR:00000CB8
MSR arm7.MSRInstruction{ .source_operand = 8, .sbo = 15, .field_mask = arm7.FieldMask{ .c = 1, .x = 0, .s = 0, .f = 1 }, ._tag1 = 2, .r = 1, ._tag2 = 2, .i = 0, ._tag3 = 0, .cond = arm7.Condition.AL } (E169F008), m=arm7.RegisterMode.FastInterrupt, operand=60000013, spsr prev=60000013, new=60000013
info(aica): arm7: (FastInterrupt) [0C6C] E24EE004 - sub lr,lr,#004         - SP:0000B1D8 - LR:00000CB8
info(aica): arm7: (FastInterrupt) [0C70] E1B0F00E - movs pc,lr             - SP:0000B1D8 - LR:00000CB4
restore_cpsr()
Setting CPSR from current mode arm7.RegisterMode.FastInterrupt to 60000013: arm7.CPSR{ .m = arm7.RegisterMode.Supervisor, .t = false, .f = false, .i = false, ._ = 0, .v = false, .c = true, .z = true, .n = false }
Changing mode from arm7.RegisterMode.FastInterrupt to arm7.RegisterMode.Supervisor
Saved SPSR for arm7.RegisterMode.Supervisor: arm7.CPSR{ .m = arm7.RegisterMode.FastInterrupt, .t = false, .f = true, .i = true, ._ = 0, .v = false, .c = true, .z = true, .n = false }
info(aica): arm7: (Supervisor) [0CB4] E92D8000 - stmdb sp!, {pc}        - SP:0000B100 - LR:00000000
info(aica): arm7: (Supervisor) [0CB8] E1A00000 - mov r0,r0              - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [0CBC] EA00153F - b 0x5504               - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61C0] E28F5C7D - add r5,pc,#7D00        - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61C4] E2855088 - add r5,r5,#088         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61C8] E595000C - ldr r0,[r5, #0xC]      - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61CC] E2800001 - add r0,r0,#001         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61D0] E585000C - str r0,[r5, #0xC]      - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61D4] E5956008 - ldr r6,[r5, #0x8]      - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61D8] E3560000 - cmp r6,#000            - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61DC] CA00001E - bgt 0x80               - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61E0] E28F0C7A - add r0,pc,#7A00        - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61E4] E2800068 - add r0,r0,#068         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61E8] E3A03010 - mov r3,#010            - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61EC] E5D01000 - ldrb r1,[r0]           - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F0] E3110080 - tst r1,#080            - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F4] 0A00000F - beq 0x44               - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6238] E2800030 - add r0,r0,#030         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [623C] E2533001 - subs r3,r3,#001        - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6240] 1AFFFFE9 - bne 0xffffffac         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61EC] E5D01000 - ldrb r1,[r0]           - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F0] E3110080 - tst r1,#080            - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F4] 0A00000F - beq 0x44               - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6238] E2800030 - add r0,r0,#030         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [623C] E2533001 - subs r3,r3,#001        - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6240] 1AFFFFE9 - bne 0xffffffac         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61EC] E5D01000 - ldrb r1,[r0]           - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F0] E3110080 - tst r1,#080            - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F4] 0A00000F - beq 0x44               - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6238] E2800030 - add r0,r0,#030         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [623C] E2533001 - subs r3,r3,#001        - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6240] 1AFFFFE9 - bne 0xffffffac         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61EC] E5D01000 - ldrb r1,[r0]           - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F0] E3110080 - tst r1,#080            - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F4] 0A00000F - beq 0x44               - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6238] E2800030 - add r0,r0,#030         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [623C] E2533001 - subs r3,r3,#001        - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6240] 1AFFFFE9 - bne 0xffffffac         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61EC] E5D01000 - ldrb r1,[r0]           - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F0] E3110080 - tst r1,#080            - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F4] 0A00000F - beq 0x44               - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6238] E2800030 - add r0,r0,#030         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [623C] E2533001 - subs r3,r3,#001        - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6240] 1AFFFFE9 - bne 0xffffffac         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61EC] E5D01000 - ldrb r1,[r0]           - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F0] E3110080 - tst r1,#080            - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F4] 0A00000F - beq 0x44               - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6238] E2800030 - add r0,r0,#030         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [623C] E2533001 - subs r3,r3,#001        - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6240] 1AFFFFE9 - bne 0xffffffac         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61EC] E5D01000 - ldrb r1,[r0]           - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F0] E3110080 - tst r1,#080            - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F4] 0A00000F - beq 0x44               - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6238] E2800030 - add r0,r0,#030         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [623C] E2533001 - subs r3,r3,#001        - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6240] 1AFFFFE9 - bne 0xffffffac         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61EC] E5D01000 - ldrb r1,[r0]           - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F0] E3110080 - tst r1,#080            - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F4] 0A00000F - beq 0x44               - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6238] E2800030 - add r0,r0,#030         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [623C] E2533001 - subs r3,r3,#001        - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6240] 1AFFFFE9 - bne 0xffffffac         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61EC] E5D01000 - ldrb r1,[r0]           - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F0] E3110080 - tst r1,#080            - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F4] 0A00000F - beq 0x44               - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6238] E2800030 - add r0,r0,#030         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [623C] E2533001 - subs r3,r3,#001        - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6240] 1AFFFFE9 - bne 0xffffffac         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61EC] E5D01000 - ldrb r1,[r0]           - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F0] E3110080 - tst r1,#080            - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F4] 0A00000F - beq 0x44               - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6238] E2800030 - add r0,r0,#030         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [623C] E2533001 - subs r3,r3,#001        - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6240] 1AFFFFE9 - bne 0xffffffac         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61EC] E5D01000 - ldrb r1,[r0]           - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F0] E3110080 - tst r1,#080            - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F4] 0A00000F - beq 0x44               - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6238] E2800030 - add r0,r0,#030         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [623C] E2533001 - subs r3,r3,#001        - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6240] 1AFFFFE9 - bne 0xffffffac         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61EC] E5D01000 - ldrb r1,[r0]           - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F0] E3110080 - tst r1,#080            - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F4] 0A00000F - beq 0x44               - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6238] E2800030 - add r0,r0,#030         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [623C] E2533001 - subs r3,r3,#001        - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6240] 1AFFFFE9 - bne 0xffffffac         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61EC] E5D01000 - ldrb r1,[r0]           - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F0] E3110080 - tst r1,#080            - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F4] 0A00000F - beq 0x44               - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6238] E2800030 - add r0,r0,#030         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [623C] E2533001 - subs r3,r3,#001        - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6240] 1AFFFFE9 - bne 0xffffffac         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61EC] E5D01000 - ldrb r1,[r0]           - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F0] E3110080 - tst r1,#080            - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F4] 0A00000F - beq 0x44               - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6238] E2800030 - add r0,r0,#030         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [623C] E2533001 - subs r3,r3,#001        - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6240] 1AFFFFE9 - bne 0xffffffac         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61EC] E5D01000 - ldrb r1,[r0]           - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F0] E3110080 - tst r1,#080            - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F4] 0A00000F - beq 0x44               - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6238] E2800030 - add r0,r0,#030         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [623C] E2533001 - subs r3,r3,#001        - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6240] 1AFFFFE9 - bne 0xffffffac         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61EC] E5D01000 - ldrb r1,[r0]           - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F0] E3110080 - tst r1,#080            - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [61F4] 0A00000F - beq 0x44               - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6238] E2800030 - add r0,r0,#030         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [623C] E2533001 - subs r3,r3,#001        - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6240] 1AFFFFE9 - bne 0xffffffac         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6244] E1B06006 - movs r6,r6             - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6248] 0A000005 - beq 0x1c               - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [6264] E8BD8000 - ldmia sp!, {pc}        - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [0CC0] E92D8000 - stmdb sp!, {pc}        - SP:0000B100 - LR:00000000
info(aica): arm7: (Supervisor) [0CC4] E1A00000 - mov r0,r0              - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [0CC8] EA000007 - b 0x24                 - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [0CEC] E59C002C - ldr r0,[r12, #0x2C]    - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [0CF0] E2800001 - add r0,r0,#001         - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [0CF4] E58C002C - str r0,[r12, #0x2C]    - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [0CF8] E59C0180 - ldr r0,[r12, #0x180]   - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [0CFC] E59A10AC - ldr r1,[r10, #0xAC]    - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [0D00] E1500001 - cmp r0,r1              - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [0D04] 858A00AC - strhi r0,[r10, #0xAC]  - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [0D08] E5DC0026 - ldrb r0,[r12, #0x26]   - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [0D0C] E2500001 - subs r0,r0,#001        - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [0D10] E5CC0026 - strb r0,[r12, #0x26]   - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [0D14] 1A000005 - bne 0x1c               - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [0D30] E8BD8000 - ldmia sp!, {pc}        - SP:0000B0FC - LR:00000000
info(aica): arm7: (Supervisor) [0CCC] E10F0000 - mrs r0, CPSR           - SP:0000B100 - LR:00000000
info(aica): arm7: (Supervisor) [0CD0] E38000C0 - orr r0,r0,#0C0         - SP:0000B100 - LR:00000000
info(aica): arm7: (Supervisor) [0CD4] E129F000 - msr CPSR_cf, r0        - SP:0000B100 - LR:00000000
Setting CPSR from current mode arm7.RegisterMode.Supervisor to 800000D3: arm7.CPSR{ .m = arm7.RegisterMode.Supervisor, .t = false, .f = true, .i = true, ._ = 0, .v = false, .c = false, .z = false, .n = true }
info(aica): arm7: (Supervisor) [0CD8] E3A00000 - mov r0,#000            - SP:0000B100 - LR:00000000
info(aica): arm7: (Supervisor) [0CDC] E5CC0003 - strb r0,[r12, #0x3]    - SP:0000B100 - LR:00000000
info(aica): arm7: (Supervisor) [0CE0] E3A00080 - mov r0,#080            - SP:0000B100 - LR:00000000
info(aica): arm7: (Supervisor) [0CE4] E58B00A4 - str r0,[r11, #0xA4]    - SP:0000B100 - LR:00000000
info(aica): arm7: (Supervisor) [0CE8] EAFFFFD8 - b 0xffffff68           - SP:0000B100 - LR:00000000
info(aica): arm7: (Supervisor) [0C50] E3A00001 - mov r0,#001            - SP:0000B100 - LR:00000000
info(aica): arm7: (Supervisor) [0C54] E5CB0504 - strb r0,[r11, #0x504]  - SP:0000B100 - LR:00000000
info(aica): arm7: (Supervisor) [0C58] E5CB0504 - strb r0,[r11, #0x504]  - SP:0000B100 - LR:00000000
info(aica): arm7: (Supervisor) [0C5C] E5CB0504 - strb r0,[r11, #0x504]  - SP:0000B100 - LR:00000000
info(aica): arm7: (Supervisor) [0C60] E5CB0504 - strb r0,[r11, #0x504]  - SP:0000B100 - LR:00000000
info(aica): arm7: (Supervisor) [0C64] E8BD41FF - ldmia sp!, {r0,r1,r2,r3,r4,r5,r6,r7,r8,lr} - SP:0000B100 - LR:00000000
info(aica): arm7: (Supervisor) [0C68] E169F008 - msr SPSR_cf, r8        - SP:0000B128 - LR:00000000
MSR arm7.MSRInstruction{ .source_operand = 8, .sbo = 15, .field_mask = arm7.FieldMask{ .c = 1, .x = 0, .s = 0, .f = 1 }, ._tag1 = 2, .r = 1, ._tag2 = 2, .i = 0, ._tag3 = 0, .cond = arm7.Condition.AL } (E169F008), m=arm7.RegisterMode.Supervisor, operand=00000000, spsr prev=600000D1, new=00000000
PC: 00000C68
LR: 00000000
SP: 0000B128
R0: 00000000   R8: 00000000
R1: 00000000   R9: 00000000
R2: 00000000   R10: 00000000
R3: 00000000   R11: 00000000
R4: 00000000   R12: 0000B200
R5: 00000000   R13: 0000B128
R6: 00000000   R14: 00000000
R7: 00000000   R15: 00000C70
   [00000C28] E59FA4D4 ldr r10,[pc, #0x4D4]
   [00000C2C] E3A00001 mov r0,#001
   [00000C30] E5CC0008 strb r0,[r12, #0x8]
   [00000C34] E14F8000 mrs r8, SPSR
   [00000C38] E92D41FF stmdb sp!, {r0,r1,r2,r3,r4,r5,r6,r7,r8,lr}
   [00000C3C] E5DB0500 ldrb r0,[r11, #0x500]
   [00000C40] E3500002 cmp r0,#002
   [00000C44] 0A00003A beq 0xf0
   [00000C48] E3500001 cmp r0,#001
   [00000C4C] 0A000008 beq 0x28
   [00000C50] E3A00001 mov r0,#001
   [00000C54] E5CB0504 strb r0,[r11, #0x504]
   [00000C58] E5CB0504 strb r0,[r11, #0x504]
   [00000C5C] E5CB0504 strb r0,[r11, #0x504]
   [00000C60] E5CB0504 strb r0,[r11, #0x504]
   [00000C64] E8BD41FF ldmia sp!, {r0,r1,r2,r3,r4,r5,r6,r7,r8,lr}
 > [00000C68] E169F008 msr SPSR_cf, r8
   [00000C6C] E24EE004 sub lr,lr,#004
   [00000C70] E1B0F00E movs pc,lr
info(aica): arm7: (Supervisor) [0C6C] E24EE004 - sub lr,lr,#004         - SP:0000B128 - LR:00000000
PC: 00000C6C
LR: FFFFFFFC
SP: 0000B128
R0: 00000000   R8: 00000000
R1: 00000000   R9: 00000000
R2: 00000000   R10: 00000000
R3: 00000000   R11: 00000000
R4: 00000000   R12: 0000B200
R5: 00000000   R13: 0000B128
R6: 00000000   R14: FFFFFFFC
R7: 00000000   R15: 00000C74
   [00000C2C] E3A00001 mov r0,#001
   [00000C30] E5CC0008 strb r0,[r12, #0x8]
   [00000C34] E14F8000 mrs r8, SPSR
   [00000C38] E92D41FF stmdb sp!, {r0,r1,r2,r3,r4,r5,r6,r7,r8,lr}
   [00000C3C] E5DB0500 ldrb r0,[r11, #0x500]
   [00000C40] E3500002 cmp r0,#002
   [00000C44] 0A00003A beq 0xf0
   [00000C48] E3500001 cmp r0,#001
   [00000C4C] 0A000008 beq 0x28
   [00000C50] E3A00001 mov r0,#001
   [00000C54] E5CB0504 strb r0,[r11, #0x504]
   [00000C58] E5CB0504 strb r0,[r11, #0x504]
   [00000C5C] E5CB0504 strb r0,[r11, #0x504]
   [00000C60] E5CB0504 strb r0,[r11, #0x504]
   [00000C64] E8BD41FF ldmia sp!, {r0,r1,r2,r3,r4,r5,r6,r7,r8,lr}
   [00000C68] E169F008 msr SPSR_cf, r8
 > [00000C6C] E24EE004 sub lr,lr,#004
   [00000C70] E1B0F00E movs pc,lr
   [00000C74] E3A000D4 mov r0,#0D4
info(aica): arm7: (Supervisor) [0C70] E1B0F00E - movs pc,lr             - SP:0000B128 - LR:FFFFFFFC
restore_cpsr()
Setting CPSR from current mode arm7.RegisterMode.Supervisor to 00000000: arm7.CPSR{ .m = arm7.RegisterMode.thread 39488 panic: invalid enum value
H:\Software\zig\0.13.0-dev.351+64ef45eb0\files\lib\std\fmt.zig:539:37: 0x965479 in formatType__anon_19832 (Deecy.exe.obj)
                try writer.writeAll(@tagName(value));
                                    ^
H:\Software\zig\0.13.0-dev.351+64ef45eb0\files\lib\std\fmt.zig:608:31: 0x950040 in formatType__anon_19662 (Deecy.exe.obj)
                try formatType(@field(value, f.name), ANY, options, writer, max_depth - 1);
                              ^
H:\Source\Deecy\libs\arm7\src\arm7.zig:519:24: 0x90270c in set_cpsr (Deecy.exe.obj)
        std.debug.print("Setting CPSR from current mode {any} to {X:0>8}: {any}\n", .{ self.cpsr.m, @as(u32, @bitCast(cpsr)), cpsr });
                       ^
H:\Source\Deecy\libs\arm7\src\arm7_interpreter.zig:597:37: 0x8d7827 in handle_data_processing (Deecy.exe.obj)
            if (inst.s == 1 and inst.rd == 15) {
                                    ^
H:\Source\Deecy\src\dreamcast.zig:399:27: 0x83ede8 in tick_peripherals (Deecy.exe.obj)
        try self.tick_aica(cycles);
                          ^
H:\Source\Deecy\src\main.zig:200:50: 0x895c85 in main (Deecy.exe.obj)
                        cycles += try dc.tick_jit();
                                                 ^
H:\Software\zig\0.13.0-dev.351+64ef45eb0\files\lib\std\start.zig:497:75: 0x89f3bd in main (Deecy.exe.obj)
    return callMainWithArgs(@as(usize, @intCast(c_argc)), @as([*][*:0]u8, @ptrCast(c_argv)), envp);
                                                                          ^
H:\Software\zig\0.13.0-dev.351+64ef45eb0\files\lib\libc\mingw\crt\crtexe.c:267:0: 0x96fec0 in __tmainCRTStartup (crt2.obj)
    mainret = _tmain (argc, argv, envp);

H:\Software\zig\0.13.0-dev.351+64ef45eb0\files\lib\libc\mingw\crt\crtexe.c:188:0: 0x96ff15 in mainCRTStartup (crt2.obj)
  ret = __tmainCRTStartup ();

???:?:?: 0x7ff9e1221ed6 in ??? (KERNEL32.DLL)
???:?:?: 0x7ff9e233a95b in ??? (ntdll.dll)
run
└─ run Deecy failure
Senryoku commented 2 months ago

Fixed with 3b83160