npetersen2
commented
4 years ago After much more thinking, another idea for this (which supersedes the above ideas):
We could push the computation into the FPGA even more... We would tell the FPGA we want a voltage of specific magnitude, theta, and omega. It would then use this information to compute the stationary voltage command for each PWM update event... this would allow us to update PWM at Tsw, which is faster than Ts.
This would basically just be moving the DQ transform (inverse) into the FPGA so the FPGA can synchronize it to the PWM updates.
It seems the nominal operation of the AMDC is with SiC power stacks which can switch much faster than the control rate of the C code (e.g. control rate
1/Ts = Fs = 10kHz, PWM switching freq1/Tsw = Fsw = 100kHz).Some applications can benefit from more fine-grained PWM duty ratio updates than Ts... ideally, every Tsw. We can give the user this option by extending the PWM IP in the FPGA! I have two ideas for implementing this:
Use a "DMA" style approach where the user configures a memory buffer which contains PWM duty ratio commands. Every switching event, the FPGA reads the next entry in the buffer and uses it. This allows the user to forward project their voltage commands to account for machine rotation (very important at high speeds and/or fast electrical dynamics) and load them into the buffer each Ts.
If the above approach is too hard, simply setting a register in the FPGA with a duty ratio delta might be enough. Then, the FPGA adds this delta to the current duty ratio before each PWM update event. Nominally, this is zero, but the user can use it if needed.