Severson-Group / AMDC-Firmware

Embedded system code (C and Verilog) which runs the AMDC Hardware
http://docs.amdc.dev/firmware
BSD 3-Clause "New" or "Revised" License
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CAN REV-A Firmware #193

Closed psinha25 closed 2 years ago

psinha25 commented 3 years ago

This PR is to merge the CAN REV-A board's IP and firmware into develop. This PR contains the necessary IP block and user application firmware to drive the CAN expansion board. Specifically, it contains:

Originally, a Xilinx provided CAN IP block was going to be used. Due to licensing issues, a bitstream couldn't be generated with this IP block. Thus, given that there are two CAN peripherals baked into the silicon of the Zync-7000 SoC, these peripherals are used and routed to the GPIO expansion ports via EMIO.

Documentation about the CAN drivers can be found here.

npetersen2 commented 3 years ago

Comments on the drv/can.h and drv/can.c files

Configuration:

Compilation Config:

Packet Tx: (assuming only support standard IDs, not extended)

Packet Rx:

psinha25 commented 3 years ago

@npetersen2

All the changes you've requested have been made. Please look to can.c and can.h. Furthermore, please take a look at the default values for the baud rate and the bit timing register bits in can.h. Currently, these defaults are not what we are wanting. I am struggling to understand what the defaults should be. Any suggestions?

psinha25 commented 3 years ago

@npetersen2 I've updated the default values in can.h for the Bit Timing Register (BTR) and the Baud Rate Prescalar Register (BRPR) to have a default bit rate of 500kbps assuming a 200 MHz clock while adhering to the CANOpen specs. Furthermore, I've formatted the code to pass the linter. Please take a look and let me know if there are any other changes to make? Otherwise, I believe this is ready to merge.

npetersen2 commented 3 years ago

@psinha25 can you confirm the CAN peripheral can operate at 200MHz clock? If I recall, it was limited to the 10s of MHz nominally.

psinha25 commented 3 years ago

@npetersen2 Does the AMDC not operate at a 200 MHz clock? Given that, the baud rate prescalar and bit timing register are set with the specific defaults to create 500 kbps.

npetersen2 commented 3 years ago

Correct, the main FPGA clock domain is 200Mhz, however, I believe there is a separate clock which runs the CAN peripheral


From: Prasoon Sinha @.> Sent: Thursday, April 29, 2021 10:16:59 PM To: Severson-Group/AMDC-Firmware @.> Cc: Nathan Petersen @.>; Mention @.> Subject: Re: [Severson-Group/AMDC-Firmware] CAN REV-A Firmware (#193)

@npetersen2https://github.com/npetersen2 Does the AMDC not operate at a 200 MHz clock? Given that, the baud rate prescalar and bit timing register are set with the specific defaults to create 500 kbps.

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psinha25 commented 3 years ago

@npetersen2 Ah interesting. I read through the clock section for the CAN peripheral in the Zynq-7000 Reference Manual and understand what you are saying now. I've updated the defaults in can.h. Please take a look and also read the comments. There I specify why the value are the way they are.

npetersen2 commented 3 years ago

@psinha25 great, thanks for the updates