Closed codecubepi closed 1 year ago
@codecubepi is this PR ready for review?
Can you confirm this works on both REV D and REV E hardware?
@npetersen2 @elsevers
@codecubepi is this PR ready for review?
Can you confirm this works on both REV D and REV E hardware?
This is now confirmed working on both REV D and REV E hardware... yay!
@codecubepi please run the clang
auto formatter: see https://github.com/Severson-Group/AMDC-Firmware/blob/v1.0.x/CONTRIBUTING.md#code-formatting
There is a nice extension to VS Code for this
@npetersen2
I believe I have addressed all of your feedback, please review my changes and comments.
Can you remember to show me which VS Code extension you use for the clang formatter in our next meeting?
@npetersen2
Ready for re-review. I think everything is much cleaner now.
@codecubepi actually, this issue is what you built for the GPIO direct IP block: https://github.com/Severson-Group/AMDC-Firmware/issues/244
@npetersen2 @elsevers
Final functionality verification is good on both REV D and REV E. I think I'm ready for this to be merged with approval.
Relevant repository issues have been linked for automatic closure and tracking
This PR is a request to merge in the additions to the GPIO ports for both the REV D and REV E AMDC.
Changes to existing AMDC REV X block designs:
REV E
gp3io_mux
IP has been expanded from 4:1 to 8:1 in each of the GPIO hierarchy blocks.gpio_direct
IP block has been added in each of the four GPIO port hierarchy blocks (for a total of four).REV D
gpio_mux
IP has been expanded from 4:2 to 8:2 in the top level block design.gpio_direct
blocks have been added in the top level hierarchy and connected to thegpio_mux
. If the REV D user desired, both REV D expansion ports could be driven by thesegpio_direct
IP blocks.GPIO_DIRECT IP Block
IP Block
The GPIO_DIRECT IP is a new block with two registers: one read, one write.
The three least-signirficant bits of the read register are determined by the digital voltage on the in pins of the connected GPIO port (after differential -> single conversion). The C code driver can be used to read these three digital values.
The three least-signirficant bits of the write register are responsible for determining the digital voltage on the out pins of the connected GPIO port (before single -> differential conversion). The C code driver can be used to set these three digital values.
Driver C Code
The driver C code (located in
sdk/app_cpu1/common/drv/gpio_direct.c
) gives a layer of abstraction by providing functions that the user can call to read, write, or toggle a given Port/Pin:Command Interface
In addition to the driver C code, a serial command interface has been provided in
sdk/app_cpu1/common/sys/cmd/cmd_hw.c
, as this IP block adds hardware functionality. See here.Additionally, another subcommand option has been added to the
hw mux
command:hw mux gpio list
This command will list which IP device is which when selecting which device to drive a GPIO port.
To-Do: