Closed npetersen2 closed 1 year ago
Building off of #127, I found that the PWM duty ratios are only latched on the bottom of the PWM carrier, not the top.
Since triangle carrier PWM is symmetrical, we should be latching on both peak and valley.
Eventually, this should be user configurable, but for now, let's just latch as fast as possible (i.e., both top and bottom).
This requires one line of Verilog code change:
https://github.com/Severson-Group/AMDC-Firmware/blob/v1.0.x/ip_repo/amdc_inverters_1.0/hdl/amdc_inverters_v1_0_S00_AXI.v#L953
Should be:
if ((carrier_low | carrier_high) & pwm_en) begin
Building off of #127, I found that the PWM duty ratios are only latched on the bottom of the PWM carrier, not the top.
Since triangle carrier PWM is symmetrical, we should be latching on both peak and valley.
Eventually, this should be user configurable, but for now, let's just latch as fast as possible (i.e., both top and bottom).
TODO
This requires one line of Verilog code change:
https://github.com/Severson-Group/AMDC-Firmware/blob/v1.0.x/ip_repo/amdc_inverters_1.0/hdl/amdc_inverters_v1_0_S00_AXI.v#L953
Should be: