Rewrite Eddy Current Sensor FPGA & Drivers

[codecubepi]

This PR is a request to merge in the new version of the Kaman Eddy Current Sensor FPGA and C drivers, This applies to both the REV D and REV E AMDC. This resolves #302.

Changes to AMDC block designs:

The amdc_eddy_current_sensor IP block has had new ports added to it. These additions apply to both REV E and REV D:

• enable: The new enable input replaces what previously a register-level setting, with an enable bit being written to in a configuration register. Because of this change, the corresponding C driver functions have been removed. For now, this port has been connected to a constant HIGH.

• pwm_carrier_high & pwm_carrier_low: Because one aim of this re-write is to sync the sampling to the PWM carrier to reduce EMI problems, these signals from the top-level block-design need to be passed into the updated IP.

• done: A done output signal is added that can be used in other IP blocks in the design. It goes high after the SPI master has requested the conversion AND has had valid data transmitted back to be read by the C driver functions.

• debug: A three-wide output that can be connected to FPGA output ports for viewing signals on scope during debugging.

REV E

REV D

New IP Blocks

This PR does not add any new IP blocks, it only provides revisions to the existing eddy_current_sensor IP.

Driver C Code

The driver C code (located in /sdk/app_cpu1/common/drv/eddy_current_sensor.c) gives a layer of abstraction by providing functions that the user can call to initialize and read the eddy current sensor data.

OLD

void eddy_current_sensor_init(void);

void eddy_current_sensor_enable(uint32_t base_addr);
void eddy_current_sensor_disable(uint32_t base_addr);

void eddy_current_sensor_set_sample_rate(uint32_t base_addr, double sample_rate);
void eddy_current_sensor_set_divider(uint32_t base_addr, uint8_t divider);

double eddy_current_sensor_read_x_voltage(uint32_t base_addr);
double eddy_current_sensor_read_y_voltage(uint32_t base_addr);

NEW

void eddy_current_sensor_init(void);

void eddy_current_sensor_trigger_on_pwm_high(uint32_t base_addr);
void eddy_current_sensor_trigger_on_pwm_low(uint32_t base_addr);
void eddy_current_sensor_trigger_on_pwm_both(uint32_t base_addr);
void eddy_current_sensor_trigger_on_pwm_clear(uint32_t base_addr);

void eddy_current_sensor_set_timing(uint32_t base_addr, uint32_t sclk_freq_khz, uint32_t propogation_delay_ns);

double eddy_current_sensor_read_x_voltage(uint32_t base_addr);
double eddy_current_sensor_read_y_voltage(uint32_t base_addr);

The enable driver function has been removed, as the IP sampling is enabled by a module input now as decribed above.

The set_sample_rate and set_divider driver functions have been removed, the sampling rate is now synced to the PWM carrier instead of the old free-running method.

The trigger_on_pwm driver functions have been added, which allow the user to configure in their C code if they want the sampling to occur on the PWM carrier's max, min, or both.

The set_timing driver function has been added:

• It allows the user to change the SPI clock rate, with acceptable frequencies range from 1 kHz to 10 MHz (due to the single/differential ICs).
• It also allows the user to define the propogation delay of the Kaman adapter board filtering. This is necessary so that the MISO line sampling properly aligns with the center of the data bits.

Finally, the init driver function has changed. Previously, it configured the eddy_current_sensor to sample at a rate of 20 kHz. It now configures the IP to sample on the PWM carrier's peak, and sets the SCLK frequency to 2 MHz.

Command Interface

The eddy current sensor did not previous support any serial commands, but due to the new configutation options, the following new commands were created:

• eddy trigger <port> <HIGH|LOW|BOTH>: Trigger the eddy current sensor to sample on the PWM carrier's peak, valley, or both
• eddy timing <port> <sclk_freq_khz> <prop_delay_ns>: The desired SCLK frequency (kHz) and one-way delay of the adapter board (ns)

Documentation:

These new changes have been documented in this IP block's README.

[codecubepi]

@npetersen2

So I think I have a theory of what's happening now... I can show you on the scope next week, but I think sampling right on the falling edge of SCLK is too early. It's catching a previous bit or something that is sometimes high and sometimes low. I will have to find someway to delay the samples so they don't happen too soon.

[codecubepi]

Hey @codecubepi , this is a to-do:

• [x] Regenerate REV E bitstream to verify that the new fixes in spi_master.v are good.
• [x] Use Xilinx serial terminal to figure out why the eddy current hw commands are returning INVALID_ARGS (and run the c-lang formatter)
• [x] Verify that the default frequencies in eddy_current_sensor_init() work.
• [x] Do testing on multiple different PWM and SCLK frequencies, make sure nothing gets stuck and only good data is returned
• [x] Once the functionality is ALL verified, check the comments in the .v and .c files, some of the frequencies may have changed.
• [x] Once REV E looks all good, update the bd/bitstream one final time to disconnect the debug output of the IP block I instead added the debug connections to all ports
• [x] Update REV D Block Design
• [ ] Test on REV D (?)
• [x] Finish up this PR

[codecubepi]

Things to look at in the lab with @npetersen2 on Monday:

• [x] Is the "start too soon" trigger that cancels the current read behaviour okay? Early triggers no longer cancel the current transaction
• [x] Why does running SCLK really fast mess with the propogation delay? You need to change the propogation delay when calling set_timing() to get the samples to occur at the correct time.
• [ ] Should I make a table with PWM Carrier Frequencies and Trigger Conditions, that gives good SCLK frequencies and propogation delays to use?

[codecubepi]

I'm restoring the branch so I can open a new PR on it. This new PR will update the IP to version 2.0 and update the AMDC REV D block design.

See #307