I/O management in FPGA

[npetersen2]

• [ ] #324

• • Extend all AMDC sensor IP (e.g., ADC) to support sampling “trigger” + “done” output

• Create new “Timing Manager” IP core

  • Interfaces between PWM generator and all sensor IP to manage trigger/done signals
  • User configurable for “enabled” sensor inputs and timing specs/ratios
  • Keeps track of timing for sensors to report back to user (e.g., acquisition time per sensor)