Add interrupt support in timing manager IP core

[annikaolson]

Sub-issue of #324.

• [x] Read more about PL to PS interrupts to understand how they are configured with Vivado https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/PS-PL-Interrupts
• [x] Follow first half of this tutorial: https://github.com/k0nze/zedboard_pl_to_ps_interrupt_example to add interrupt support in the FPGA logic.
• [x] #339
• [x] Modify existing timer logic to now implement current logic (e.g. connect new logic to interrupt)
  • [x] Delete existing timer IP core (two parts: not used, other is for scheduler isr which we will be replacing)
  • [x] Add new concat block and hook up to PS