Add sensor "enable" logic to timing manager IP + driver

Severson-Group / AMDC-Firmware

Embedded system code (C and Verilog) which runs the AMDC Hardware

http://docs.amdc.dev/firmware

BSD 3-Clause "New" or "Revised" License

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Add sensor "enable" logic to timing manager IP + driver #345

Closed annikaolson closed 7 months ago

annikaolson commented 8 months ago

Modify the existing logic in the FPGA to send an enable signal to each of the sensors. There should (currently) be 6: ADC, encoder, eddy 0, eddy 1, eddy 2, and eddy 3. This should come from the user specified enable bits from timing_manager.c. The default should be no sensors enabled.

8-bit integer, each bit represents a sensor -> 1 is enable, 0 is disabled.