Brought to me by @aravind075, and discussed by @npetersen2 , @annikaolson , and myself in our firmware meeting. The following is an addition for the v1 firmware, and this should be propogated into the v2 firmware as well.
The status lines on the DB-15 Power Stack inverter connectors are designed to be used as either single-ended outputs or single-ended inputs. However, when declared as inputs, the data coming into the AMDC on the physical wire is not accessible via the current firmware. The inv_status_mux_1.0 IP here does assign these lines as inout, but does not place the data in a register to be read by the Xil_In() function in the C code driver here. The input data is output from the inv_status_mux IP in the block design as deviceX_out, but these ports do not connect out to anything else in the block design.
To add the functionality to read these inputs, the data input on the status lines will have to be clocked into a register (requiring update to the Verilog HDL, possibly the block design in Vivado) and to the C driver linked above.
There are various levels of effort that could be put into updating the HDL. A lot of the current code seems... questionable. The current implementation has thirty-six registers, which could be condensed down since many bits are not used. In particular, slv_reg32 - slv_reg35 are each 32-bit registers, a single bit of each is used. See the README for register details.
Brought to me by @aravind075, and discussed by @npetersen2 , @annikaolson , and myself in our firmware meeting. The following is an addition for the
v1firmware, and this should be propogated into thev2firmware as well.The status lines on the DB-15 Power Stack inverter connectors are designed to be used as either single-ended outputs or single-ended inputs. However, when declared as inputs, the data coming into the AMDC on the physical wire is not accessible via the current firmware. The
inv_status_mux_1.0IP here does assign these lines asinout, but does not place the data in a register to be read by theXil_In()function in the C code driver here. The input data is output from the inv_status_mux IP in the block design asdeviceX_out, but these ports do not connect out to anything else in the block design.To add the functionality to read these inputs, the data input on the status lines will have to be clocked into a register (requiring update to the Verilog HDL, possibly the block design in Vivado) and to the C driver linked above.
There are various levels of effort that could be put into updating the HDL. A lot of the current code seems... questionable. The current implementation has thirty-six registers, which could be condensed down since many bits are not used. In particular,
slv_reg32-slv_reg35are each 32-bit registers, a single bit of each is used. See the README for register details.HDL Code
https://github.com/Severson-Group/AMDC-Firmware/blob/b665cbcb9a27b3b69baedb2887e5dc634ca86145/ip_repo/amdc_inv_status_mux_1.0/hdl/amdc_inv_status_mux_v1_0_S00_AXI.v#L854-L864
REV E Block Design