Merge new AMDS driver and other FPGA changes back into v1.3-staging

[codecubepi]

For the new AMDS Interface:

Resolves the following from #365 :

• [x] Created new amdc_amds IP from old motherboard IP
• [x] Updated trigger and done logic in new IP to be compatible with the Timing Manager
• [x] Add amds_X_done and amds_X_en ports (X is 0-3) to amdc_timing_manager IP
• [x] Update and rename driver for AMDS (from motherboard)
• [x] Update and rename command interface for AMDS (from motherboard)

To minimize the number of branches that are making FPGA changes and updating the block designs for each REV, the following have also been addressed in this branch PR:

Resolves the following from #381 and #383 :

• [x] Corrected logic in timing manager IP that was sending out too many triggers
• [x] Added new logic and C code that enables users to request that a single trigger be asserted by the timing manager at the next PWM high/low

Resolves the following from #380 :

• [x] Remove the pwm_carrier high/low ports from the Eddy Current Sensor IP

After all the changes above were addressed:

• [x] Updated REV F block design
• [x] #388

Will probably push until we are completely done with verifying v1.3 on REV F:

• [ ] Updated REV E block design
• [ ] Updated REV D block design
• [ ] Once all block designs are updated, delete the legacy motherboard driver IP

[codecubepi]

The plan is for @annikaolson to rebase the user/annikaolson/something branch off of v1.3-staging once this PR is merged, so she can make some necessary FPGA changes of her own.

This rebase will require merging some C code that we've both changed, so I'm happy to help resolve any conflicts.

[codecubepi]

I think this is ready for a re-review all.