search

Severson-Group / AMDC-Firmware

Embedded system code (C and Verilog) which runs the AMDC Hardware
http://docs.amdc.dev/firmware
BSD 3-Clause "New" or "Revised" License
33 stars 6 forks source link

Final fixes to new AMDS Driver: Invalid Data and Timeout #394

Closed codecubepi closed 5 months ago

codecubepi commented 5 months ago

Resolves some final issues in the AMDS driver:

Invalid Data Issue

This was addressed by adjusting the flop timing of the data lines coming into the AMDS driver.

The state machine in adc_uart_rx.v is also a little more robust in how it determines the validity of each packet. Previously, if the first packet sent across a data line was corrupt (failed the parity check), the parent SM would give up and not even direct the child SM in uart_rx.v to read the following packets. This is no longer the case, the parent SM will keep going through the normal state cycle (HEADER -> MSB -> LSB) even if an earlier packet becomes corrupted. The transistion from the DONE state back to IDLE is only made once all packets have been read.

Finally, a timer was added which allows the user to read the latency in microseconds from the trigger (and SYNC_ADC being sent to the AMDS) to the first packet appearing on the data line.

Strange Timeout Behaviour

This issue was not fully resolved in this PR. I attempted to restructure the timeout system so that there are two timeout events: a long timeout event if the first packet does not appear on the data line within 10us of the trigger (this was easy to add using the new timer mentioned above), and a second timeout for each individual UART start bit.

The driver is timing out (yay), but sometimes the SMs inexpicably are still running and incrementing the data corrupt counter when they should be stuck in IDLE.

The merge plan is to:

  1. Have @npetersen2 review these latest changes required to get the AMDS stuff working, then we'll merge into v1.3-staging
  2. Open a new PR on behalf of @annikaolson (to resolve any conflicts in #392 ), do a hand merge, then do some basic testing to ensure lights still blink etc. I'll review the code changes, then let's merge to v1.3-staging
  3. Once both are into merged into staging, Nathan will work with me in the lab to build the full demo of the system with a uInverter and really stress test the full system. This will expose any remaining bugs to fix before final release of v1.3.0
codecubepi commented 5 months ago

This PR fixes #389. However, I was not able to fully address the weird time out behaviour. See this issue comment: https://github.com/Severson-Group/AMDC-Firmware/issues/393#issuecomment-2142338423

codecubepi commented 5 months ago

Thanks! I will get this merged into the staging branch.