Updates to Inverter/PWM IP

Severson-Group / AMDC-Firmware

Embedded system code (C and Verilog) which runs the AMDC Hardware

http://docs.amdc.dev/firmware

BSD 3-Clause "New" or "Revised" License

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Updates to Inverter/PWM IP #400

Closed codecubepi closed 5 months ago

codecubepi commented 5 months ago

Created README for IP
Added new modes to control when new duty ratios are latched in, set in user_config.h:
- Mode 0: Next Timing Manager Trigger
- Mode 1: Next carrier peak/valley
- Mode 2: Immediately on next FPGA clock rise
Added ability to enable/disable a single inverter leg outside of global PWM enable for @anirudhupadhyaya .

Resolves #398

codecubepi commented 5 months ago

@npetersen2

I think this is ready for review. I might want some tips on how to test these new features, I'm sure I can apply some of the changes to our bench setup.

codecubepi commented 5 months ago

Severson-Group / AMDC-Firmware

Updates to Inverter/PWM IP #400

Testing the new per-`leg_enable` functionality:

Captured with only leg one enabled:

Captured with legs one and two enabled:

Severson-Group / AMDC-Firmware

Updates to Inverter/PWM IP #400

Testing the new per-leg_enable functionality:

Captured with only leg one enabled:

Captured with legs one and two enabled:

Testing the new per-`leg_enable` functionality: