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Severson-Group / AMDS

Voltage and Current Sense Board
BSD 3-Clause "New" or "Revised" License
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Mainboard firmware architecture description #36

Closed npetersen2 closed 6 months ago

npetersen2 commented 3 years ago

This PR adds a markdown doc which describes the AMDS mainboard firmware design. This will be helpful to future users who want to understand the system performance.

Read the main doc I added here.

GnomeTek commented 3 years ago

Suggestion of updating Sync signals to " 'Sync_xxx' shall be a square wave". A square wave/pulse is a requirement for proper timing, right? The use of "normally" suggest I could feed this a triangle wave and the system would maintain the described timing latency.

For TX signals 'DATAx' the UART is described, how is the ADC data packed into the 8bit transmission? is ADC data 8bit, 32bit? Byte order in UART transmission might be helpful also.

npetersen2 commented 3 years ago

@ngadiyar93 Good idea for adding a doc about the AMDC side of the AMDS interface.

I think this doesn't belong in this repo, but instead, in the AMDC repos -- probably AMDC-Firmware since there is a full driver in the FPGA to interface to the AMDS.

Can you create an issue in AMDC-Firmware which explains the need for this? Thanks.

npetersen2 commented 3 years ago

@GnomeTek See updated doc. I added comments on data packing/ordering in UART stream.

npetersen2 commented 6 months ago

This ended up getting merged into the docs.amd.dev website, see: https://docs.amdc.dev/accessories/amds/firmware/