search

SiEPIC / SiEPIC-Tools

Package for KLayout to add integrated optics / silicon photonics functionality (waveguides, netlist extraction, circuit simulations, etc)
Other
184 stars 92 forks source link

Minor change to Line 89 of layout.py #165

Closed ANT-Jocelyn closed 2 years ago

ANT-Jocelyn commented 2 years ago

Suggest change to Line 89 to allow length to be calculated for any layer, not just layers named "Waveguides". The current wording causes a failure in the waveguide generation of the Applied Nanotools PDK since we call our Si layer "Device Layer Full Etch".

lukasc-ubc commented 2 years ago

Hi @ANT-Jocelyn

Unfortunately this line is in the loop, and your change would always be True since we define layer = layout.layer(TECHNOLOGY[layers[lr]]).

Calculating the waveguide length is a bit tricky especially for slot waveguides, where you have two geometries. Hence we created 'Waveguide' as a virtual layer that isn't fabricated, and only used for taking measurements.

Since you only have one waveguide layer, you can also have the 'Waveguide' layer have the exact same Layer/Datatype as your "Device Layer Full Etch" layer. You can put the "Waveguide" layer in the "SiEPIC" category, where we have things like PinRec, PinRecM, DevRec, FbrTgt, FP. You can also make that layer hidden if you want. Make sure add the Waveguide layer in the Waveguides.XML file.

ANT-Jocelyn commented 2 years ago

Okay, thanks for taking a look at this @lukasc-ubc!