SiEPIC / SiEPIC-Tools

Package for KLayout to add integrated optics / silicon photonics functionality (waveguides, netlist extraction, circuit simulations, etc)
Other
181 stars 90 forks source link

reduce PIN length in SiEPIC? #167

Closed joamatab closed 2 years ago

joamatab commented 2 years ago

Hi!

Im building a pure scripted layout in gdsfactory that is compatible with SiEPIC tools verification and netlist extraction flow

What do you think of making the PINs 2nm wide? so that small waveguides do not have issues with the connectivity check

Im having issues with 90nm long waveguides because the pins are too long (100nm)

image

image

@thomasdorch @lukasc-ubc