Using SiEPIC PDK (v0.4.24), I made a test layout with an array of (4) GC_SiN_TE_1550_8degOxide_BB GCs. With this updated version of the PDK, the array of (4) GCs fits within the 600um height of the design area. However, after making SiN Strip TE 1550nm, w=750nm waveguide loopbacks, DRC found "Disconnected pin" issues at each GC. See the attached GDS file.
Using SiEPIC PDK (v0.4.24), I made a test layout with an array of (4) GC_SiN_TE_1550_8degOxide_BB GCs. With this updated version of the PDK, the array of (4) GCs fits within the 600um height of the design area. However, after making SiN Strip TE 1550nm, w=750nm waveguide loopbacks, DRC found "Disconnected pin" issues at each GC. See the attached GDS file.
4GC_test.zip