Firmware compilation error with always_latch

[cbespin]

Adding always_latch in CG_MOD_neg.v and CG_MOD_pos.v throws errors when compiling existing projects with Vivado. Presumably, because it is not a standard verilog keyword.

[themperek]

It is standard: https://fpga.mit.edu/6205/_static/F23/documentation/1800-2017.pdf ;-)

Try changing names to CG_MOD_neg.sv and CG_MOD_pos.sv (not sure about it).

[cbespin]

This is the SystemVerilog standard, not a 1364-X one, right? I guess it will work as .sv, but will nevertheless break existing projects where the .v file is used as source.