SiLab-Bonn / basil

A data acquisition framework in Python and Verilog.
BSD 3-Clause "New" or "Revised" License
40 stars 29 forks source link

Fix firmware compilation error #223

Closed cbespin closed 6 months ago

cbespin commented 6 months ago

This PR fixes #219, removing the SystemVerilog always_latch statement that crashes existing firmware projects where the respective files are listed in the included modules in Vivado. The verilator metacomment disables the warning that is raised at compilation time which stops execution of the test.

In a future (major) version, the SystemVerilog syntax should be adopted and the files renamed to *.sv which requires changes in depending firmware projects.