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SiLab-Bonn / pyBAR

Bonn ATLAS Readout in Python - A readout software for FEI4 pixel detectors
BSD 3-Clause "New" or "Revised" License
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Treat PlsrDAC ringing #58

Closed DavidLP closed 8 years ago

DavidLP commented 8 years ago

Some FE-I4 (especially after irradiation) show a ringing PlsrDAC:

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If the injection loop is too quick the injected charge can change leading to measured higher noise and a charge that depends on the injection speed. We should add an additional injection delay with std. value = 0 to all scans using the PlsrDAC to be able to make the injecion speed slower.

laborleben commented 8 years ago

In the picture there is no ringing before the pulse. Can you explain?

laborleben commented 8 years ago

OK, I try to explain: The standard delay is around 80us and the next pulse would be still inside the dangerous region (10us/dev). So this plot either show the first pulse or injections with already extended delay.

DavidLP commented 8 years ago

Yes, long delay. I misscalculated. We can have 400 us injection delay with our current FPGA cmd sequenzer implementation (16000 * 25 ns). That is sufficient. So we just have to add a parameter in software.

DavidLP commented 8 years ago

Just to make it clear how the analog scan (and thus all other scans) with std. settings (3rd mask) looks like: capture

DavidLP commented 8 years ago

The ringing can be fixed by increasing the OP amp bias of the:

IV converter op amp

capture

responsible for the slow return to baseline.

The configuration for a not ringing PlsrDAC is: PlsrVgOpAmp = 150

Disclamer: I think PlsrVgOpAmp is this OP amps bias. There is also another gain 2 OP amp to increase the rail-to-rail amplitude. It is not mentioned anywhere (?), neither in schematics nor the manual wich op amp is adressed by PlsrVgOpAmp. So the explanation is an educated guess.

DavidLP commented 8 years ago

Since that does not have to be fixed in software I close this issue.