I found some issues with F6.7. It's a long story, but basically I was using MartyPC to fill in the register state after divide exceptions since the test rig didn't handle them at the time, but MartyPC had a regression in 8 bit signed division. Here's the PR with the fix:
I found some issues with F6.7. It's a long story, but basically I was using MartyPC to fill in the register state after divide exceptions since the test rig didn't handle them at the time, but MartyPC had a regression in 8 bit signed division. Here's the PR with the fix:
https://github.com/TomHarte/ProcessorTests/pull/73